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    Optical packet switching based on traffic properties
    2.
    发明授权
    Optical packet switching based on traffic properties 有权

    公开(公告)号：US10701466B1

    公开(公告)日：2020-06-30

    申请号：US16382541

    申请日：2019-04-12

    Applicant: Nokia Solutions and Networks Oy

    Inventor： Brice Leclerc ,  Olivier Marcé ,  Dominique Chiaroni ,  Bogdan Uscumlic

    IPC: H04J14/00 ,  H04Q11/00

    Abstract: A node is configured for deployment in an optical network. The node includes an analog switch for routing an optical packet between input ports and output ports. The node also includes digital processing circuitry configured to generate first configuration information based on the optical packet prior to providing the optical packet to the analog switch. The analog switch is configured to route the optical packet between the input ports and the output ports based on the first configuration information in response to the optical packet arriving at the node in a first time interval. The optical packet is not processed by the digital processing circuit or results of processing are not used to configure the analog switch during a second time interval. The analog switch routes the optical packet between the input and output ports based on second configuration information during the second time interval.

    Network device including trained neural network
    3.
    发明授权
    Network device including trained neural network 有权

    公开(公告)号：US12155566B2

    公开(公告)日：2024-11-26

    申请号：US17572884

    申请日：2022-01-11

    Applicant: Nokia Solutions and Networks Oy

    Inventor： Bogdan Uscumlic ,  Yu-Chia Tseng

    IPC: H04L45/00 ,  G06F18/214 ,  G06N3/047 ,  H04L45/42

    Abstract: A device includes a transceiver and processing circuitry. The transceiver is configured to receive an input packet having an input header and forward an output packet having an output header. The processing circuitry is configured to parse the input header, determine recommendations for forwarding a payload of the input packet using a trained neural network and based on the parsed input header, and process the input packet and generate the output packet with the output header based on the recommendations and available resources.

    Inter-packet communication of machine learning information
    4.
    发明授权
    Inter-packet communication of machine learning information 有权

    公开(公告)号：US11528347B2

    公开(公告)日：2022-12-13

    申请号：US16911671

    申请日：2020-06-25

    Applicant: Nokia Solutions and Networks Oy

    Inventor： Bogdan Uscumlic ,  Gopalasingham Aravinthan ,  Lionel Natarianni

    IPC: H04L69/22 ,  H04L49/101 ,  H04L47/24 ,  H04L47/62

    Abstract: A network switch includes one or more queues to hold packets received from a first input flow and a second input flow. The network switch also includes a packet communication switch configured to access a first header of a first packet in the one or more queues and a second header of a second packet in the one or more queues. The first header includes first machine learning (ML) information that represents a first set of state transition probabilities under a set of actions performed at the network switch. The second header includes second ML information that represents a second set of state transition probabilities under the set of actions performed at the network switch. The packet communication switch is configured to selectively modify the first header or the second header based on a comparison of the first ML information and the second ML information.

    Dynamic shared protection using redundant network paths
    6.
    发明授权
    Dynamic shared protection using redundant network paths 有权

    公开(公告)号：US10972382B2

    公开(公告)日：2021-04-06

    申请号：US16432783

    申请日：2019-06-05

    Applicant: Nokia Solutions and Networks Oy

    Inventor： Bogdan Uscumlic ,  Gopalasingham Aravinthan

    IPC: H04L12/707 ,  H04L12/26 ,  H04L12/823 ,  H04L12/861 ,  H04W84/18

    Abstract: A node in a mesh network includes insertion circuitry to selectively delay first packets prior to insertion in a mesh network by a first time interval corresponding to a maximum failure detection time interval for the mesh network based on whether a failure has been detected in the mesh network. The node includes reception circuitry configured to selectively delay second packets received from the mesh network by a second time interval depending on whether the failure has been detected. The second time interval equals a maximum latency for the mesh network minus a sum of the maximum failure detection time interval and a propagation time along a working path. If a failure is detected, the second packets are delayed by a third time interval determined based on the maximum latency, the maximum failure detection time interval, and a propagation time along a backup path for the working path.

    Dedicated memory buffers for supporting deterministic inter-FPGA communication
    9.
    发明授权
    Dedicated memory buffers for supporting deterministic inter-FPGA communication 有权

    公开(公告)号：US11416399B2

    公开(公告)日：2022-08-16

    申请号：US16911680

    申请日：2020-06-25

    Applicant: Nokia Solutions and Networks Oy

    Inventor： Andrea Enrici ,  Bogdan Uscumlic

    IPC: G06F12/0806

    Abstract: A server includes a field programmable gate array (FPGA) partitioned into a set of partial reconfiguration (PR) slots and a memory that supports a set of logical buffers. A deterministic application request module (DARM) receives application requests to allocate the set of reconfiguration slots to one or more tenants and the one or more tenants configure the allocated reconfiguration slot to perform tasks. The DARM stores data associated with the application request in a first logical buffer from the set of logical buffers. A reconfiguration slot scheduling (RSS) module identifies a first reconfiguration slot from the set of reconfiguration slots and associates the first reconfiguration slot with the first logical buffer. A reconfiguration slot initialization (RSI) module reconfigures the first reconfiguration slot to perform the tasks based on the data stored in the first logical buffer.

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