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公开(公告)号：US5333032A
公开(公告)日：1994-07-26
申请号：US667987
申请日：1991-03-12
IPC分类号： H03K19/173 , G06F17/50 , G06F15/60
CPC分类号： G06F17/505
摘要： In a system for transforming input circuit information into information of a logic circuit composed of actual elements, a schematic diagram of a logic circuit composed of actual elements is displayed. A timing check is executed on the displayed logic circuit. A delay adjustment portion of the displayed schematic diagram is designated. A timing adjustment is executed by the system on the designated delay adjustment portion, and thereby the logic circuit is transformed into a second logic circuit composed of actual elements.
摘要翻译： 在将输入电路信息变换成由实际元件构成的逻辑电路的信息的系统中，显示由实际元件构成的逻辑电路的示意图。 在显示的逻辑电路上执行定时检查。 指定所示示意图的延迟调整部分。 由系统在指定的延迟调整部分执行定时调整，从而将逻辑电路变换为由实际元件组成的第二逻辑电路。
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2.发明授权Circuit transformation system, circuit transformation method, inverted logic generation method, and logic design system 失效电路转换系统，电路转换方法，倒置逻辑生成方法和逻辑设计系统
公开(公告)号：US5043914A
公开(公告)日：1991-08-27
申请号：US249555
申请日：1988-09-26
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , Y10S706/919 , Y10S706/921
摘要： Circuit transformation of a first circuit constituted by a first set of elements into a logically equivalent second circuit constituted by a second set of elements is effected by selecting a candidate rule from a knowledge base memory. The knowledge base memory stores therein transformation rules expressed by a condition part and a conclusion part. The condition part of a candidate rule is matched to circuit data stored in a working memory. The application condition of the candidate rules is determined, and the candidate rule is applied to the circuit data of the working memory for transforming the circuit after confirmation of the establishment of the application condition. The knowledge base memory stores therein concise transformation rules including at least one of main transformation rules, subordinate transformation rules, logic negation rules and logic equivalence rules.
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公开(公告)号：US5668965A
公开(公告)日：1997-09-16
申请号：US616763
申请日：1996-03-15
CPC分类号： G06F17/5045 , G06F3/0482
摘要： In a data processor such as a CAD system for LSI design, a hierarchical structure of a plurality of objects each having a circuit data is represented in a relation between a window on a menu screen and a plurality of figure blocks on the window. One of the plural figure blocks on the window is represented in a different window so as to represent a multi-hierarchical structure of the objects, and a block figure group is arranged on the different window. A user selects, using a mouse, an object to be processed on a menu screen representing a floor plan.
摘要翻译： 在诸如用于LSI设计的CAD系统的数据处理器中，具有电路数据的多个对象的分层结构以菜单屏幕上的窗口和窗口上的多个图块之间的关系来表示。 窗口中的多个图形块中的一个在不同的窗口中表示，以便表示对象的多层次结构，并且块图组被布置在不同的窗口上。 用户使用鼠标在表示平面图的菜单屏幕上选择要处理的对象。
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公开(公告)号：US5892678A
公开(公告)日：1999-04-06
申请号：US943524
申请日：1997-10-03
CPC分类号： G06F17/5045 , Y10S706/921
摘要： An improved LSI design automation system includes: an input unit, a circuit component storage unit, a circuit component selection unit, a design method decision unit, a design process unit, and a component entry unit. The input unit receives LSI function and performance information as a requirements specification and LSI component configuration information. The circuit component storage unit collectively stores a circuit data item, design method information items, and performance information items, as a circuit component. The circuit component selection unit selects a circuit component from the circuit component storage unit for implementation of a desired circuit. The design method decision unit selects an optimum design method information item from the design method information items held by each circuit component. The design process unit generates, modifies, and evaluates a circuit. The component entry unit enters a result of the modification made during the design and a newly generated circuit component into the circuit component storage unit.
摘要翻译： 改进的LSI设计自动化系统包括：输入单元，电路元件存储单元，电路元件选择单元，设计方法判定单元，设计处理单元和元件输入单元。 输入单元接收LSI功能和性能信息作为需求规格和LSI组件配置信息。 电路部件存储部将电路数据项目，设计方法信息项和性能信息项集中存储为电路部件。 电路元件选择单元从电路元件存储单元中选择电路元件，以实现期望的电路。 设计方法判定单元从由各电路部件保持的设计方法信息项中选择最优设计方法信息项。 设计过程单元生成，修改和评估电路。 组件输入单元将在设计期间进行的修改的结果和新产生的电路组件输入到电路部件存储单元中。
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公开(公告)号：US5519630A
公开(公告)日：1996-05-21
申请号：US210468
申请日：1994-03-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Together with circuit data of circuit elements, there is stored, in a memory device, external specification information of each of the circuit elements, the information including (i) function information of each of the terminals of the circuit elements and (ii) selection information representing a wiring condition for each of the terminals. When the element arrangement and external specification information of a circuit to be designed, are entered, pieces of external specification information are compared with one another to obtain pairs of wiring candidates of a circuit which connects, to one another, the circuit elements of the circuit to be designed. Based on the pairs of wiring candidates, there is generated wiring information which satisfies each wiring condition. Based on the pieces of wiring information thus generated, there are automatically generated circuit data of the circuit to be designed.
摘要翻译： 与电路元件的电路数据一起，在存储器件中存储每个电路元件的外部规格信息，该信息包括（i）电路元件的每个端子的功能信息和（ii）选择信息 代表每个终端的布线条件。 当要设计的电路的元件布置和外部指定信息被输入时，将外部指定信息彼此进行比较，以获得将电路的电路元件彼此连接的电路的布线候补对 设计。 基于配线候补对，生成满足各布线条件的布线信息。 基于如此生成的布线信息，自动生成要设计的电路的电路数据。
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公开(公告)号：US5359539A
公开(公告)日：1994-10-25
申请号：US52240
申请日：1993-04-20
CPC分类号： G06F17/505
摘要： A plurality of types of circuit transformation rules have condition parts and conclusion parts. An inference control knowledge includes a knowledge related to a method of inferring the circuit transformation rules and a knowledge related to a relation between the circuit transformation rules. The circuit transformation rules are compiled into circuit transformation programs by use of the inference control knowledge. Already-existing programs include a procedural process of a logic design and various functions necessary for an execution of the circuit transformation programs. The circuit transformation programs and the already-existing programs are combined into a logic design program. A circuit transformation process is executed in accordance with the logic design program.
摘要翻译： 多种类型的电路转换规则具有条件部分和结论部分。 推理控制知识包括与推断电路变换规则的方法有关的知识以及与电路变换规则之间的关系相关的知识。 电路转换规则通过使用推理控制知识编译成电路转换程序。 已经存在的程序包括逻辑设计的过程过程和执行电路转换程序所需的各种功能。 电路转换程序和已经存在的程序被组合成逻辑设计程序。 根据逻辑设计程序执行电路变换处理。
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公开(公告)号：US5563800A
公开(公告)日：1996-10-08
申请号：US427696
申请日：1995-04-24
CPC分类号： G06F17/505
摘要： A logic synthesis unit generates configuration data of a virtual logic circuit composed of virtual elements, or logic gates each of which carries only a functional definition, in order to realize a logic circuit functional description fed through an input unit. A logic transformation unit, referring to a standard cell library, performs the allocation of real elements for implementation to respective virtual elements to transform the virtual logic circuit into a real logic circuit having the same function as the virtual logic circuit. Then the logic transformation unit, referring to a timing analysis unit, selects a particular real element with a smallest driving capacity from among the real elements in the library performing the same function as an object virtual element and satisfying both fan-out restrictions and delay constraints, and allocates the real element thus selected to the virtual element. Configuration data of the resulting real logic circuit are output in the forms of circuit diagrams, real element connection information lists, and the like through an output unit.
摘要翻译： 逻辑合成单元产生由虚拟元件组成的虚拟逻辑电路的配置数据，或者每个仅携带功能定义的逻辑门，以实现通过输入单元馈送的逻辑电路功能描述。 参考标准单元库的逻辑变换单元执行用于实现的实际元件的分配到各个虚拟元件，以将虚拟逻辑电路转换成具有与虚拟逻辑电路相同功能的实际逻辑电路。 然后，逻辑变换单元参考定时分析单元从执行与对象虚拟元件相同功能的库中的实际元素中选择具有最小驱动能力的特定实数元素，并且满足扇出限制和延迟约束 ，并将如此选择的真实元素分配给虚拟元素。 所得到的真实逻辑电路的配置数据通过输出单元以电路图，实际元件连接信息列表等的形式输出。
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8.发明授权Logic design system for creating circuit configuration by generating parse tree from hardware description language and optimizing text level redundancy thereof 失效逻辑设计系统，用于通过从硬件描述语言生成解析树并优化其文本级冗余来创建电路配置
公开(公告)号：US5146583A
公开(公告)日：1992-09-08
申请号：US734113
申请日：1991-07-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , Y10S706/921
摘要： An apparatus and method for translating a function description of a circuit presented in hardware description language includes parsing the function description of the circuit to generate a parse tree. The structure of the parse tree is deformed to optimize the test level redundancy of the function description to thereby generate a deformed parse tree. The deformed parse tree is then translated into function blocks representing a hardware configuration of the circuit set forth by the function description.
摘要翻译： 用于翻译以硬件描述语言呈现的电路的功能描述的装置和方法包括解析电路的功能描述以生成解析树。 解析树的结构变形以优化功能描述的测试级冗余，从而生成变形的解析树。 然后将变形的解析树转换成表示由功能描述阐述的电路的硬件配置的功能块。
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公开(公告)号：US5886912A
公开(公告)日：1999-03-23
申请号：US557316
申请日：1995-11-14
申请人： Jiro Miyake , Kazuki Ninomiya , Tamotsu Nishiyama
发明人： Jiro Miyake , Kazuki Ninomiya , Tamotsu Nishiyama
CPC分类号： H03H17/0283
摘要： A plurality of processing elements are connected in cascade so as to constitute a single signal processing apparatus. The signal processing apparatus has a first path for transferring an input data signal and a second path for transferring a processing result of the input data signal. Each of the processing elements has a first input disposed on the first path, a data holding circuit for holding the data signal supplied through the first input, a product-sum circuit for executing a product-sum operation between the data signal held in the data holding circuit and another data signal, a second input disposed on the second path so as to supply the other data signal to the product-sum circuit, a result register for holding the result of the operation calculated by the product-sum circuit and supplying the held result of the operation to the second path, an output selecting circuit for supplying either one of the data signal held in the data holding circuit and the result of the operation held in the result register, and a processing control circuit for controlling respective operations of the data holding circuit, product-sum circuit, result register, and output selecting circuit. Since a route extending from the result register to the output selecting circuit forms a bypass from the second path to the first path, a flexible process can be performed by the signal processing apparatus by using or not using the bypass depending on control information.
摘要翻译： 多个处理元件级联连接成构成单个信号处理装置。 信号处理装置具有用于传送输入数据信号的第一路径和用于传送输入数据信号的处理结果的第二路径。 每个处理元件具有设置在第一路径上的第一输入端，用于保持通过第一输入端提供的数据信号的数据保持电路，用于在保持在数据中的数据信号之间执行乘积和运算的乘积和电路 保持电路和另一数据信号，第二输入设置在第二路径上，以便将其他数据信号提供给乘积和电路;结果寄存器，用于保持由乘积和电路计算的运算结果，并提供 保持对第二路径的操作结果，输出选择电路，用于提供保持在数据保持电路中的数据信号中的任一个和结果寄存器中保存的操作结果;以及处理控制电路，用于控制 数据保持电路，积和电路，结果寄存器和输出选择电路。 由于从结果寄存器延伸到输出选择电路的路由形成从第二路径到第一路径的旁路，所以可以由信号处理装置根据控制信息使用或不使用旁路来执行灵活处理。
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公开(公告)号：US5751374A
公开(公告)日：1998-05-12
申请号：US618610
申请日：1996-03-20
CPC分类号： H04N5/46 , H04N7/0152 , H04N9/642 , H04N5/907
摘要： A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.
摘要翻译： 协处理器被并入包括CPU，指令高速缓存，数据存储器，总线控制器，中断控制部分和DMA控制器的处理器中。 该协处理器具有并行产品总和运算部分，比较器，I / O寄存器部分和产品总和因子寄存器部分。 在输入侧提供的帧存储器存储每像素数字化的MUSE或NTSC信号。 DMA控制输入侧帧存储器和数据存储器之间的数据传送以及在输出侧提供的帧存储器与数据存储器之间的数据传送。 存储在数据存储器中的像素数据根据广播系统通过基于软件的乘积因子的切换进行处理。
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