公开(公告)号：US20110181271A1

公开(公告)日：2011-07-28

申请号：US13014130

申请日：2011-01-26

申请人： Norio CHUJO ,  Takehito Kamimura

发明人： Norio CHUJO ,  Takehito Kamimura

IPC分类号： G01R19/00 ,  H03F1/00 ,  H03F3/45 ,  H03G3/00 ,  G06G7/14

CPC分类号： H03F3/45183 ,  H03F2203/45652 ,  H03F2203/45702 ,  H03G5/28

摘要： A peaking circuit according to the present invention includes amplifiers connected in multiple stages and feedback circuits for feedback to an input from two or more output points with different gains as seen from the input. The peaking circuit is configured to be able to change an amount of feedback of the feedback circuits.

摘要翻译： 根据本发明的峰化电路包括多级连接的放大器和反馈电路，用于从输入端看到具有不同增益的两个或多个输出点的输入反馈。 峰值电路被配置为能够改变反馈电路的反馈量。

公开(公告)号：US20140125398A1

公开(公告)日：2014-05-08

申请号：US14122623

申请日：2012-05-24

申请人： Wen Li ,  Norio Chujo ,  Masami Makuuchi ,  Takehito Kamimura

发明人： Wen Li ,  Norio Chujo ,  Masami Makuuchi ,  Takehito Kamimura

IPC分类号： H03K19/0175

CPC分类号： H03K19/0175 ,  H01L2224/48137 ,  H01L2924/181 ,  H03F1/52 ,  H03F3/195 ,  H03F3/211 ,  H03F3/3022 ,  H03F2200/189 ,  H03K19/017509 ,  H01L2924/00012

摘要： Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).

摘要翻译： 提供可以输出超过工艺耐压的电压并满足所需设备性能（高速和高电压）的驱动器集成电路的结构。 差分输入电路，电平移位电路和输出电路通过相同的工艺制造并且被分配和布置在具有不同衬底电位（子电位）的三个或更多个芯片上。 通过对芯片的基板设置不同的施加电压，可以提供大于工艺耐受电压的输出电压（参见图2）。

公开(公告)号：US09698783B2

公开(公告)日：2017-07-04

申请号：US14122623

申请日：2012-05-24

申请人： Wen Li ,  Norio Chujo ,  Masami Makuuchi ,  Takehito Kamimura

发明人： Wen Li ,  Norio Chujo ,  Masami Makuuchi ,  Takehito Kamimura

IPC分类号： H03K19/0175 ,  H03F1/52 ,  H03F3/195 ,  H03F3/21 ,  H03F3/30

CPC分类号： H03K19/0175 ,  H01L2224/48137 ,  H01L2924/181 ,  H03F1/52 ,  H03F3/195 ,  H03F3/211 ,  H03F3/3022 ,  H03F2200/189 ,  H03K19/017509 ,  H01L2924/00012

摘要： Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).

公开(公告)号：US08067984B2

公开(公告)日：2011-11-29

申请号：US12797121

申请日：2010-06-09

申请人： Takehito Kamimura ,  Norio Chujo

发明人： Takehito Kamimura ,  Norio Chujo

IPC分类号： H03G3/10

CPC分类号： H03G1/0088 ,  H03F3/72 ,  H03F2203/7206 ,  H03G1/0029 ,  H03G3/3084

摘要： There is provided a variable gain circuit system which is inductorless and capable of achieving a high gain and a wide band by elements for achieving variable gain to prevent decreasing a gain or deteriorating the band. The variable gain circuit includes: transistors; a resistor connected as a load of each transistor; a voltage source applying a bias voltage to each gate of the transistors; a switch selectively connecting the voltage source or a ground potential to each gate of the transistors in accordance with gain setting; and a current source connected to a common input. A drain of each transistor is connected to an input of a circuit in a subsequent stage.

摘要翻译： 提供了一种可变增益电路系统，其是无电感的并且能够通过用于实现可变增益的元件实现高增益和宽带，以防止降低增益或使频带恶化。 可变增益电路包括：晶体管; 作为每个晶体管的负载连接的电阻器; 对晶体管的每个栅极施加偏置电压的电压源; 开关根据增益设置选择性地将电压源或接地电位连接到晶体管的每个栅极; 以及连接到公共输入的电流源。 每个晶体管的漏极在后续阶段连接到电路的输入端。