公开(公告)号：US08406581B2

公开(公告)日：2013-03-26

申请号：US13382459

申请日：2010-06-02

申请人： Saori Hamamura ,  Naoki Matsushima ,  Madoka Minagawa ,  Satoshi Kaneko ,  Norio Chujo ,  Yasunobu Matsuoka ,  Toshiki Sugawara ,  Tsutomu Kono

发明人： Saori Hamamura ,  Naoki Matsushima ,  Madoka Minagawa ,  Satoshi Kaneko ,  Norio Chujo ,  Yasunobu Matsuoka ,  Toshiki Sugawara ,  Tsutomu Kono

IPC分类号： G02B6/12

CPC分类号： G02B6/4201 ,  G02B6/424 ,  G02B6/4244 ,  G02B6/4246 ,  G02B6/4257 ,  G02B6/428 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/3512 ,  Y10T29/49146

摘要： A photoelectric composite wiring module, being superior in performances and mass-productivity thereof, and a transmission apparatus of applying that therein are provided.Optical devices 2a and 2b are disposed on a circuit board 1, so that they are optically coupled with optical guides 11 formed on the circuit board 1, wherein a filet-like resin is formed on a side surface of a bump, which is formed on side surfaces or/and upper portions of the optical devices, on an upper layer thereof being compressed a resin film to be adhered thereon, thereby forming an insulation film 31, and an electric wiring layer 3 is laminated, so that the electrodes of the optical devices 2 and wirings of the electric wiring layer are electrically connected with, and further thereon is mounted a semiconductor element 4; thereby obtaining the structure for brining the transmission speed to be high per channel, and for preventing the power consumption from increasing. Also, it has the structure of not causing deterioration of the optical devices due to ill influences of moisture, thereby achieving high reliability. Further, it also produces an easy connecting method with a transmission apparatus, and high productivity thereof.

摘要翻译： 提供了一种性能优良，批量生产率高的光电复合布线模块以及其中应用的发送装置。 光学器件2a和2b设置在电路板1上，使得它们与形成在电路板1上的光导11光学耦合，其中在凸起的侧表面上形成file状树脂，其形成在 光学元件的侧表面或/或上部在其上层被压缩以粘附在其上的树脂膜，从而形成绝缘膜31，并且层叠电布线层3，使得光学器件的电极 器件2和布线层的布线电连接，并且其上安装有半导体元件4; 从而获得用于使传输速度提高到每个通道高的结构，并且用于防止功耗增加。 此外，其具有不会由于湿气的不良影响而导致光学元件劣化的结构，从而实现高可靠性。 此外，它还产生与传动装置的简单连接方法，并且其生产率高。

公开(公告)号：US08324925B2

公开(公告)日：2012-12-04

申请号：US13106926

申请日：2011-05-13

申请人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

发明人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

IPC分类号： H03K19/003

CPC分类号： H03K19/018521

摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

公开(公告)号：US20110181271A1

公开(公告)日：2011-07-28

申请号：US13014130

申请日：2011-01-26

申请人： Norio CHUJO ,  Takehito Kamimura

发明人： Norio CHUJO ,  Takehito Kamimura

IPC分类号： G01R19/00 ,  H03F1/00 ,  H03F3/45 ,  H03G3/00 ,  G06G7/14

CPC分类号： H03F3/45183 ,  H03F2203/45652 ,  H03F2203/45702 ,  H03G5/28

摘要： A peaking circuit according to the present invention includes amplifiers connected in multiple stages and feedback circuits for feedback to an input from two or more output points with different gains as seen from the input. The peaking circuit is configured to be able to change an amount of feedback of the feedback circuits.

摘要翻译： 根据本发明的峰化电路包括多级连接的放大器和反馈电路，用于从输入端看到具有不同增益的两个或多个输出点的输入反馈。 峰值电路被配置为能够改变反馈电路的反馈量。

公开(公告)号：US20090179666A1

公开(公告)日：2009-07-16

申请号：US12343521

申请日：2008-12-24

申请人： Norio Chujo ,  Keiichi Yamamoto ,  Hisaaki Kanai ,  Toru Yazaki

发明人： Norio Chujo ,  Keiichi Yamamoto ,  Hisaaki Kanai ,  Toru Yazaki

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H04L25/0278 ,  H04L25/028

摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, capable of improving resolution of a pre-emphasis amount without increasing power consumption or a circuit area, in which the output buffer circuit 10 has a function which includes a delay circuit 23, an inverter 22 and output buffers 3 to 7 to transmit a logical signal to a transmission line 2 and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line 2 and the output buffer 3 has a variable resistance portion 12 at an on-resistance to change a pre-emphasis amount according to a change in a variable resistance value. The output buffer 3 has a selector 20 on a forward stage and a variable resistance portion 12 at an on-resistance. The inverter 22 is configured to select a signal to be input into the output buffer 6 according to a selector logic, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.

摘要翻译： 输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，能够提高预加重量的分辨率而不增加功耗或电路面积，其中 输出缓冲电路10具有包括延迟电路23，反相器22和输出缓冲器3〜7的功能，以将逻辑信号发送到传输线2，并在发送侧产生具有四种或更多种信号电压的波形 根据传输线2的信号衰减量，输出缓冲器3具有导通电阻的可变电阻部分12，以根据可变电阻值的变化改变预加重量。 输出缓冲器3具有前级上的选择器20和导通电阻的可变电阻部分12。 反相器22被配置为根据选择器逻辑选择要输入到输出缓冲器6的信号，反转数据信号，并通过选择器逻辑的选择信号来调整抽头预加重量。

公开(公告)号：US20090085688A1

公开(公告)日：2009-04-02

申请号：US12145829

申请日：2008-06-25

申请人： Keiichi YAMAMOTO ,  Norio Chujo ,  Toru Yazaki ,  Hisaaki Kanai

发明人： Keiichi YAMAMOTO ,  Norio Chujo ,  Toru Yazaki ,  Hisaaki Kanai

IPC分类号： H03H11/30

CPC分类号： H03F3/3028 ,  H01L2924/19051 ,  H03F1/308 ,  H03F2200/447 ,  H03F2200/453 ,  H03K19/017581

摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.

摘要翻译： 在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路 计算由工作点计算电路找到的工作点处的阻抗。 阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。 这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两​​个用于高侧和低侧阻抗调节。

公开(公告)号：US20090003463A1

公开(公告)日：2009-01-01

申请号：US12099953

申请日：2008-04-09

申请人： Satoshi Muraoka ,  Norio Chujo

发明人： Satoshi Muraoka ,  Norio Chujo

IPC分类号： H04B3/00 ,  H03K19/0175

CPC分类号： H03K19/0005 ,  H03K17/164 ,  H03K19/018521 ,  H04L25/0288 ,  H04L25/03343

摘要： An output buffer circuit which transmits a logic signal to a transmission line includes a transmission pre-emphasis output circuit and a transmission pre-emphasis amount determination circuit. The transmission pre-emphasis output circuit controls a pre-emphasis amount according to an output signal from the transmission pre-emphasis amount determination circuit. The transmission pre-emphasis amount determination circuit adjusts a pre-emphasis amount and the number of pre-emphasis taps according to a pseudo loss control signal, controls a pre-emphasis amount of a transmission signal so that a signal amplitude is made smaller in a signal component with a high frequency than that of a signal component with a low frequency, and imparts signal degradation to a received waveform to realize transmission loss in a pseudo manner.

摘要翻译： 向传输线发送逻辑信号的输出缓冲电路包括发送预加重输出电路和发送预加重量确定电路。 发送预加重输出电路根据来自发送预加重量确定电路的输出信号来控制预加重量。 发送预加重量确定电路根据伪损失控制信号调整预加重量和预加重抽头的数量，控制发送信号的预加重量，使信号幅度变小 信号分量高于具有低频率的信号分量的信号分量，并且对接收到的波形施加信号劣化，以伪方式实现传输损耗。

公开(公告)号：US07358953B2

公开(公告)日：2008-04-15

申请号：US10714943

申请日：2003-11-18

申请人： Masami Makuuchi ,  Kengo Imagawa ,  Norio Chujo ,  Ritsuro Orihashi ,  Yoshitomo Arai ,  Atsushi Obuchi

发明人： Masami Makuuchi ,  Kengo Imagawa ,  Norio Chujo ,  Ritsuro Orihashi ,  Yoshitomo Arai ,  Atsushi Obuchi

IPC分类号： G09G3/36

CPC分类号： G09G3/006 ,  G09G3/3648 ,  G09G5/006 ,  G09G5/39 ,  G09G2310/027 ,  Y10S345/904

摘要： A semiconductor device having a liquid crystal driving circuit is disclosed. The driving circuit includes a digital functional unit and an analog functional unit. The digital functional unit is comprised of a display controller and a display data storage RAM, while the analog functional unit is made up of a gradation voltage generating circuit and a gradation voltage selecting circuit. The digital and analog function units are functionally divided from each other and testing of the digital function and testing of the analog function unit are performed in an overlapping manner independently from each other.

摘要翻译： 公开了一种具有液晶驱动电路的半导体器件。 驱动电路包括数字功能单元和模拟功能单元。 数字功能单元包括显示控制器和显示数据存储RAM，而模拟功能单元由灰度电压产生电路和灰度电压选择电路组成。 数字和模拟功能单元在功能上彼此划分，并且以彼此独立的重叠方式执行数字功能的测试和模拟功能单元的测试。

公开(公告)号：US20080030242A1

公开(公告)日：2008-02-07

申请号：US11831087

申请日：2007-07-31

申请人： Norio Chujo ,  Satoshi Muraoka

发明人： Norio Chujo ,  Satoshi Muraoka

IPC分类号： H03K3/00 ,  H01R13/66 ,  H03K5/12

CPC分类号： H04L25/0272 ,  H01L24/45 ,  H01L24/46 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48092 ,  H01L2224/48137 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/43 ,  H01L2924/01006

摘要： The present invention provides a differential signaling system comprising: a driver circuit that transmits a differential signal; a receiver circuit that receives the differential signal; and two or more signal lines used for the differential signal to be transmitted by the driver circuit and received by the receiver circuit, wherein the driver circuit gives an arbitrary time lag between the two signals that form the differential signal before transmitting them.

摘要翻译： 本发明提供一种差分信号系统，包括：发送差分信号的驱动电路; 接收差分信号的接收机电路; 并且用于差分信号的两条或更多条信号线由驱动器电路传输并由接收器电路接收，其中驱动器电路在发送差分信号之前形成差分信号的两个信号之间给出任意时滞。

公开(公告)号：US20070184687A1

公开(公告)日：2007-08-09

申请号：US11657462

申请日：2007-01-25

申请人： Hisaaki Kanai ,  Norio Chujo ,  Masayoshi Yagyu

发明人： Hisaaki Kanai ,  Norio Chujo ,  Masayoshi Yagyu

IPC分类号： H05K1/00

CPC分类号： H05K1/0268 ,  H05K1/0237 ,  H05K3/0047 ,  H05K3/429 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/163 ,  H05K2203/175

摘要： One of a group which is located on the side of a main surface of the circuit board than the one conductive layer of the plurality of conductive layers is used as a terminal to detect the digging depth of the through hole, and the digging of the through hole is stopped according to the change of the conductive state between the detection terminal and the through hole (or the one conductive layer which is electrically connected to this). A circuit board is formed so that the detection terminal in a group of the plurality of conductive layers contacts with the drill which dig the through hole and a group of the conductive layers except the detection terminal does not contact with the drill, respectively.

摘要翻译： 使用位于电路板的主表面侧的多个导电层的一个导电层中的一个作为端子来检测通孔的挖掘深度，并且挖掘通孔 根据检测端子和通孔（或与其电连接的一个导电层）之间的导电状态的变化来停止孔。 形成电路板，使得多个导电层中的一组中的检测端子与钻孔相接触，钻头分别钻出通孔，除了检测端子之外的一组导电层不与钻头接触。

公开(公告)号：US20050122300A1

公开(公告)日：2005-06-09

申请号：US10981715

申请日：2004-11-05

申请人： Masami Makuuchi ,  Norio Chujo ,  Kengo Imagawa ,  Ritsuro Orihashi ,  Yoshitomo Arai

发明人： Masami Makuuchi ,  Norio Chujo ,  Kengo Imagawa ,  Ritsuro Orihashi ,  Yoshitomo Arai

IPC分类号： G01R31/316 ,  G01R31/28 ,  G02F1/133 ,  G09G3/00 ,  G09G3/20 ,  G09G3/36 ,  H01L21/822 ,  H01L27/04

CPC分类号： G09G3/006 ,  G09G3/3688

摘要： A semiconductor device according to the present invention has a liquid crystal driver circuit, and when gray-scale voltage thereof is tested, the gray-scale voltage (Vx) generated in a gray-scale voltage generator circuit provided therein is compared with reference voltage (e.g., Vx+ΔV) generated for testing the gray-scale voltage and the test result is output as binarized voltage from external terminals of the semiconductor device. This can speed up the gray-scale voltage test even in the case of higher gray scale in the liquid crystal driver circuit or increased number of output terminals of the semiconductor device. Therefore, it becomes possible to reduce the time and cost required for the test.

摘要翻译： 根据本发明的半导体器件具有液晶驱动电路，并且当其灰度电压被测试时，在其中提供的灰度级电压发生器电路中产生的灰度电压（Vx）与参考电压（ 例如，用于测试灰度电压而生成的Vx + DeltaV）和测试结果作为来自半导体器件的外部端子的二值化电压输出。 即使在液晶驱动电路中较高的灰度级或半导体器件的输出端数量增加的情况下，也可以加快灰度电压测试。 因此，可以减少测试所需的时间和成本。