Wireless communication device, integrated circuit and method of timing synchronisation
    1.
    发明授权
    Wireless communication device, integrated circuit and method of timing synchronisation 有权
    无线通信设备,集成电路和定时同步方法

    公开(公告)号:US08379627B2

    公开(公告)日:2013-02-19

    申请号:US12521862

    申请日:2007-01-02

    IPC分类号: H04J3/06 H04L12/28 H04L12/56

    CPC分类号: H04L7/04 H04J3/0685

    摘要: A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronization logic operably coupled to a counter, such that data is sampled by the timing synchronization logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterized in that the timing synchronization logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronization. In particular, the inventive concept may allow a radio frequency integrated circuit to implement timing synchronization by advancing or retarding an ‘actual’ signal sent from digital baseband circuits in a 3G DigRF wireless communication device.

    摘要翻译: 无线通信设备包括第一子系统,其被布置为将数据传递到第二子系统,该第二子系统包括可操作地耦合到计数器的定时同步逻辑,使得当数据被从第二子系统传送到第二子系统时由定时同步逻辑采样 第一子系统,其中所述无线通信装置的特征在于,所述定时同步逻辑被布置成确定第一数据帧的位置,并且响应于所述定时同步逻辑启动所述计数器的计数处理并且确定第二数据帧的位置 响应于此从计数器的计数处理确定计数值,并且响应于计数值确定是否对正被传递到第二子系统的数据启动定时提前或定时延迟操作。 以这种方式,本发明的概念为无线通信设备提供了实现定时同步的机制。 具体地,本发明的概念可以允许射频集成电路通过推进或延迟在3G DigRF无线通信设备中从数字基带电路发送的实际信号来实现定时同步。

    WIRELESS COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD OF TIMING SYNCHRONISATION
    2.
    发明申请
    WIRELESS COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD OF TIMING SYNCHRONISATION 有权
    无线通信设备,集成电路和时序同步的方法

    公开(公告)号:US20100034192A1

    公开(公告)日:2010-02-11

    申请号:US12521862

    申请日:2007-01-02

    IPC分类号: H04J3/06

    CPC分类号: H04L7/04 H04J3/0685

    摘要: A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronisation logic operably coupled to a counter, such that data is sampled by the timing synchronisation logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterised in that the timing synchronisation logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronisation. In particular, the inventive concept may allow a radio frequency integrated circuit to implement timing synchronisation by advancing or retarding an ‘actual’ signal sent from digital baseband circuits in a 3G DigRF wireless communication device.

    摘要翻译: 无线通信设备包括第一子系统,其被布置为将数据传递到第二子系统,该第二子系统包括可操作地耦合到计数器的定时同步逻辑,使得当数据被从第二子系统传送到第二子系统时由定时同步逻辑采样 第一子系统,其中所述无线通信装置的特征在于,所述定时同步逻辑被布置成确定第一数据帧的位置,并且响应于所述定时同步逻辑启动所述计数器的计数处理并且确定第二数据帧的位置 响应于此从计数器的计数处理确定计数值,并且响应于计数值确定是否对正被传递到第二子系统的数据启动定时提前或定时延迟操作。 以这种方式,本发明的概念为无线通信设备提供了实现定时同步的机制。 特别地,本发明的概念可以允许射频集成电路通过推进或延迟在3G DigRF无线通信设备中从数字基带电路发送的“实际”信号来实现定时同步。

    WIRELESS COMMUNICATION UNIT, BASEBAND MODULE, RADIO FREQUENCY MODULE, WIRELESS TERMINAL AND COMPUTER PROGRAM PRODUCT
    4.
    发明申请
    WIRELESS COMMUNICATION UNIT, BASEBAND MODULE, RADIO FREQUENCY MODULE, WIRELESS TERMINAL AND COMPUTER PROGRAM PRODUCT 有权
    无线通信单元,基带模块,无线电频率模块,无线终端和计算机程序产品

    公开(公告)号:US20100311464A1

    公开(公告)日:2010-12-09

    申请号:US12600007

    申请日:2007-05-25

    IPC分类号: H04M1/00

    CPC分类号: H04B1/406 H03L7/1976

    摘要: A wireless communication unit has two or more communication modes including one or more mobile phone mode, in which mobile phone mode the wireless communication unit is able to transmit or receive wireless signals via an antenna from and/or to a mobile phone network in accordance with a communication protocol. The unit includes a baseband module and a radiofrequency module. A radiofrequency interface of the baseband module is connected to the radiofrequency module, for receiving and/or transmitting baseband signals from and/or to the radiofrequency module. The radiofrequency module includes a baseband interface, for receiving and/or transmitting the baseband signals to the baseband module and an antenna interface (AI) connectable to an antenna for receiving and/or transmitting radiofrequency signals from and/or to the antenna. A clock system is connected to the radiofrequency interface and the baseband interface. The clock system can provide a clock signal with a clock rate of to the radiofrequency interface and the baseband interface in one or more of the one or more mobile phone modes.

    摘要翻译: 无线通信单元具有包括一个或多个移动电话模式的两个或多个通信模式,其中移动电话模式,无线通信单元能够经由天线从移动电话网络和/或向移动电话网络发送或接收无线信号,根据 通信协议。 该单元包括基带模块和射频模块。 基带模块的射频接口连接到射频模块,用于从射频模块接收和/或发射基带信号。 射频模块包括用于接收和/或发送基带信号到基带模块的基带接口和可连接到天线的天线接口(AI),用于从天线接收和/或发射射频信号。 时钟系统连接到射频接口和基带接口。 时钟系统可以在一个或多个移动电话模式中的一个或多个中提供具有到射频接口和基带接口的时钟速率的时钟信号。

    Wireless Receiver for removing direct current offset component
    5.
    发明申请
    Wireless Receiver for removing direct current offset component 有权
    用于去除直流偏移分量的无线接收器

    公开(公告)号:US20070280379A1

    公开(公告)日:2007-12-06

    申请号:US11443199

    申请日:2006-05-30

    IPC分类号: H04L27/22

    CPC分类号: H04L25/06 H03D7/00

    摘要: A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.

    摘要翻译: 无线接收机包括硬件(HW)块,转换器块和数字信号处理器(DSP)。 HW块接收具有第一DC偏移分量(DCOC)的无线信号,去除第一DCOC的一部分以产生以DC为中心的残余DCOC,并产生估计残余DCOC的参数。 转换器块耦合到HW块并接收以DC为中心的残余DCOC,并将其转换为以IF为中心的残留DCOC。 DSP耦合到HW块和转换器模块,并从转换器模块接收以IF为中心的残留DCOC和来自HW模块的参数,并使用参数来消除残余DCOC,并生成基本信号 没有第一个DCOC和剩余的DCOC。

    Methods and systems for combining timing signals for transmission over a serial interface
    6.
    发明授权
    Methods and systems for combining timing signals for transmission over a serial interface 有权
    用于组合定时信号以在串行接口上​​传输的方法和系统

    公开(公告)号:US08170166B2

    公开(公告)日:2012-05-01

    申请号:US12392841

    申请日:2009-02-25

    IPC分类号: H04L7/00

    CPC分类号: H04J3/0685 H04B1/40

    摘要: Apparatus, systems, and methods are provided for transmitting messages over a serial interface. A method comprises receiving a first signal at a first time and receiving a second signal at a second time, the second time being after the first time. If a difference between the second time and the first time is less than a threshold time period, the method comprises generating a first message that is representative of the first signal and the second signal and transmitting the first message over the serial interface. In accordance with one embodiment, the threshold time period is equal to one half of an interface acquisition delay time period associated with the serial interface.

    摘要翻译: 提供了用于通过串行接口发送消息的装置,系统和方法。 一种方法包括在第一时间接收第一信号并在第二时间接收第二信号,第二时间是在第一次之后。 如果第二时间和第一时间之间的差小于阈值时间段,则该方法包括生成表示第一信号和第二信号的第一消息,并通过串行接口发送第一消息。 根据一个实施例,阈值时间周期等于与串行接口相关联的接口获取延迟时间周期的一半。

    Wireless communication unit and power control system thereof
    7.
    发明授权
    Wireless communication unit and power control system thereof 有权
    无线通信单元及其功率控制系统

    公开(公告)号:US07991367B2

    公开(公告)日:2011-08-02

    申请号:US11722293

    申请日:2004-12-23

    IPC分类号: H04B1/04

    CPC分类号: H04W52/52 H03G3/3047

    摘要: A wireless communication unit comprises a transmitter having an analogue feedback power control loop having a power control function arranged to set an output power level of the transmitter. The power control function comprises a predictor sub-system arranged to reduce sensitivity to loop latency of the analogue feedback power control loop. The use of a predictor sub-system provides reduced sensitivity to loop latency, gain variations and delay.

    摘要翻译: 无线通信单元包括具有模拟反馈功率控制环路的发射机,该模拟反馈功率控制环路具有布置成设置发射机的输出功率电平的功率控制功能。 功率控制功能包括预测器子系统,其被布置为降低模拟反馈功率控制回路的环路延迟的灵敏度。 使用预测器子系统可以降低环路延迟,增益变化和延迟的灵敏度。

    Wireless receiver for removing direct current offset component
    8.
    发明授权
    Wireless receiver for removing direct current offset component 有权
    用于去除直流偏移分量的无线接收器

    公开(公告)号:US07593485B2

    公开(公告)日:2009-09-22

    申请号:US11443199

    申请日:2006-05-30

    IPC分类号: H04L25/06

    CPC分类号: H04L25/06 H03D7/00

    摘要: A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.

    摘要翻译: 无线接收机包括硬件(HW)块,转换器块和数字信号处理器(DSP)。 HW块接收具有第一DC偏移分量(DCOC)的无线信号,去除第一DCOC的一部分以产生以DC为中心的残余DCOC,并产生估计残余DCOC的参数。 转换器块耦合到HW块并接收以DC为中心的残余DCOC,并将其转换为以IF为中心的残留DCOC。 DSP耦合到HW块和转换器模块,并从转换器模块接收以IF为中心的残留DCOC和来自HW模块的参数,并使用参数来消除残余DCOC,并生成基本信号 没有第一个DCOC和剩余的DCOC。

    SYSTEMS AND METHODS FOR ADJUSTING HEADROOM OF A POWER AMPLIFIER
    10.
    发明申请
    SYSTEMS AND METHODS FOR ADJUSTING HEADROOM OF A POWER AMPLIFIER 有权
    用于调节功率放大器的整流器的系统和方法

    公开(公告)号:US20100105343A1

    公开(公告)日:2010-04-29

    申请号:US12259867

    申请日:2008-10-28

    IPC分类号: H03F1/02 H04B1/04

    摘要: Systems and methods are provided for controlling headroom of an amplifier (e.g., in a transmitter). A method comprises obtaining a target output power for a current interval and obtaining a target headroom for a subsequent interval. The method continues by adjusting, during the current interval, the power output capability of the amplifier based on the target headroom and adjusting the input power of an input signal based on the target output power, such that the output power of the amplifier is substantially constant during the current interval as the power output capability of the amplifier is adjusted.

    摘要翻译: 提供了用于控制放大器(例如,在发射机中)的余量的系统和方法。 一种方法包括获得当前间隔的目标输出功率并获得用于后续间隔的目标余量。 该方法通过在当前时间间隔期间基于目标余量调整放大器的功率输出能力并基于目标输出功率调整输入信号的输入功率,使得放大器的输出功率基本上恒定 在当前时间间隔内,调节放大器的功率输出能力。