公开(公告)号：US09793350B1

公开(公告)日：2017-10-17

申请号：US15464512

申请日：2017-03-21

Applicant: Northrop Grumman Systems Corporation

Inventor： Roger S. Tsai ,  Sumiko L. Poust ,  Weidong Liu

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0692 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/78696

Abstract: An exemplary FET includes a base and first and second stacked layer groups each having a nonconductive layer and a semiconductive layer adjacent the nonconductive layer. Source and drain electrodes are in low resistance contact with the semiconductive layers. First and second parallel trenches extend vertically between the source and drain electrodes to create access to first and second edges, respectively, of the layers. A 3-dimensional ridge is defined by the layers between the first and second trenches. A continuous conductive side gate extends generally perpendicular to the trenches and engages the first edges, the top of the ridge and the second edges. A gate electrode is disposed in low resistance contact with the conductive side gate. The figure of merit for the FET increases as the number of layer groups increases. A plurality of parallel spaced apart ridges, all engaged by the same side gate, can be utilized.