公开(公告)号：US09793350B1

公开(公告)日：2017-10-17

申请号：US15464512

申请日：2017-03-21

Applicant: Northrop Grumman Systems Corporation

Inventor： Roger S. Tsai ,  Sumiko L. Poust ,  Weidong Liu

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0692 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/78696

Abstract: An exemplary FET includes a base and first and second stacked layer groups each having a nonconductive layer and a semiconductive layer adjacent the nonconductive layer. Source and drain electrodes are in low resistance contact with the semiconductive layers. First and second parallel trenches extend vertically between the source and drain electrodes to create access to first and second edges, respectively, of the layers. A 3-dimensional ridge is defined by the layers between the first and second trenches. A continuous conductive side gate extends generally perpendicular to the trenches and engages the first edges, the top of the ridge and the second edges. A gate electrode is disposed in low resistance contact with the conductive side gate. The figure of merit for the FET increases as the number of layer groups increases. A plurality of parallel spaced apart ridges, all engaged by the same side gate, can be utilized.

公开(公告)号：US09425110B1

公开(公告)日：2016-08-23

申请号：US14837718

申请日：2015-08-27

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Jose G. Padilla ,  Philip W. Hon ,  Shih-En Shih ,  Roger S. Tsai ,  Xianglin Zeng

IPC: H01L21/66 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/66

CPC classification number: H01L22/22 ,  H01L22/14 ,  H01L22/32 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6616 ,  H01L2223/6683 ,  H01L2225/06555 ,  H01L2225/06596

Abstract: A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

Abstract translation: 三维晶片级封装（WLP）集成电路，其包括一对相对的电路单元，其在单独的晶片上制造，所述相对电路单元已经被结合在一起以提供垂直电路冗余。 每个单独的晶片之间的集成电路在晶片被接合在一起之前进行性能测试，以便将表现良好的电路指定为有源电路单元，并且作为不活动电路单元的执行不良电路。 用于特定对集成电路的非活动电路单元用短路金属层进行金属化，以使其不可操作。 WLP集成电路在空间不相关的晶片上实现了屈服增强电路冗余方案，避免了浪费有价值的晶圆xy平面区域，由于更多的晶片面积可用于每个晶片上的不同电路，因此可以节省成本，而不是牺牲传统方面 - 电路的冗余副本。

公开(公告)号：US09793353B1

公开(公告)日：2017-10-17

申请号：US15464528

申请日：2017-03-21

Applicant: Northrop Grumman Systems Corporation

Inventor： Roger S. Tsai

IPC: H01L29/786 ,  H01L29/15 ,  H01L29/417 ,  H01L29/06 ,  H01L29/778 ,  H03F3/193 ,  H01L29/78 ,  H01L27/088 ,  H01L29/205 ,  H03F1/32 ,  H01L21/8234

CPC classification number: H01L29/152 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0692 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/7783 ,  H01L29/785 ,  H01L29/78696 ,  H03F1/3205 ,  H03F3/193 ,  H03F2200/451 ,  H03F2201/3215

Abstract: An exemplary FET includes a substrate and multiple vertically stacked layer groups with each layer group having a quantum well semiconductive layer and a nonconductive layer adjacent the first quantum well semiconductive layer. Conductive source and drain electrodes in conductive contact with the semiconductive layers. A 3-dimensional ridge of the stacked layer groups is defined between spaced apart first and second trenches which are between the source and drain electrodes. A continuous conductive side gate is disposed on the sides and top of the ridge for inducing a field into the semiconductive layers. A gate electrode is disposed in conductive contact with the conductive side gate.