公开(公告)号：US10163465B1

公开(公告)日：2018-12-25

申请号：US15680216

申请日：2017-08-18

Applicant: NOVATEK Microelectronics Corp.

Inventor： Po-Yao Ko ,  Chien-Chung Chen ,  Hsu-Yu Huang ,  Chun-Po Huang

IPC: G11C8/10 ,  G11C7/10 ,  H03F3/30

Abstract: A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.

公开(公告)号：US10826521B1

公开(公告)日：2020-11-03

申请号：US16547547

申请日：2019-08-21

Applicant: Novatek Microelectronics Corp.

Inventor： Chun-Po Huang ,  Liang-Ting Kuo ,  Yi-Shen Cheng ,  Chia-Chuan Lee ,  Soon-Jyh Chang

IPC: H03M1/46 ,  H03M1/10 ,  H03M1/12

Abstract: A successive approximation register (SAR) analog to digital converter (ADC) and a method of detecting an offset of a comparator are introduced. The SAR ADC includes a switch circuit, a comparator and a calibration circuit. The switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. The comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value. The comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value. The calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.

公开(公告)号：US20200328753A1

公开(公告)日：2020-10-15

申请号：US16547547

申请日：2019-08-21

Applicant: Novatek Microelectronics Corp.

Inventor： Chun-Po Huang ,  Liang-Ting Kuo ,  Yi-Shen Cheng ,  Chia-Chuan Lee ,  Soon-Jyh Chang

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/10

Abstract: A successive approximation register (SAR) analog to digital converter (ADC) and a method of detecting an offset of a comparator are introduced. The SAR ADC includes a switch circuit, a comparator and a calibration circuit. The switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. The comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value. The comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value. The calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.