公开(公告)号：US20230121521A1

公开(公告)日：2023-04-20

申请号：US17501985

申请日：2021-10-14

Applicant: Novatek Microelectronics Corp.

Inventor： Hao-Che Hsu ,  Chin-Tung Chan ,  Ying-Cheng Lin ,  Ren-Hong Luo

IPC: H04L25/02 ,  H03F3/45

Abstract: A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.

公开(公告)号：US12261610B2

公开(公告)日：2025-03-25

申请号：US18496908

申请日：2023-10-29

Applicant: NOVATEK Microelectronics Corp.

Inventor： Chin-Tung Chan ,  Yan-Ting Wang ,  Ren-Hong Luo ,  Chih-Wen Chen ,  Hao-Che Hsu ,  Li-Wei Lin

IPC: H03L7/099 ,  H03L7/085 ,  H03L7/23

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

公开(公告)号：US12009949B2

公开(公告)日：2024-06-11

申请号：US17501985

申请日：2021-10-14

Applicant: Novatek Microelectronics Corp.

Inventor： Hao-Che Hsu ,  Chin-Tung Chan ,  Ying-Cheng Lin ,  Ren-Hong Luo

IPC: H04L25/02 ,  H03F3/45

CPC classification number: H04L25/0272 ,  H03F3/45076 ,  H04L25/028

Abstract: A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.