-
公开(公告)号：US20170279461A1
公开(公告)日：2017-09-28
申请号：US15409478
申请日：2017-01-18
Applicant: Novatek Microelectronics Corp.
Inventor： Shih-Chun Lin , Ren-Hong Luo , Mu-Jung Chen , Yung-Cheng Lin
CPC classification number: H03M9/00 , H03K3/037 , H03K5/01 , H03K5/15046 , H03K2005/00019
Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
-
公开(公告)号：US20230121521A1
公开(公告)日：2023-04-20
申请号：US17501985
申请日：2021-10-14
Applicant: Novatek Microelectronics Corp.
Inventor： Hao-Che Hsu , Chin-Tung Chan , Ying-Cheng Lin , Ren-Hong Luo
Abstract: A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.
-
3.发明授权公开(公告)号：US09515699B2
公开(公告)日：2016-12-06
申请号：US14723449
申请日：2015-05-27
Applicant: Novatek Microelectronics Corp.
Inventor： Ren-Hong Luo , Yan-Ting Wang , Hsiang-Chi Li , Mu-Jung Chen
Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.
Abstract translation: 提供了一种用于切换其模式的双模串行传输装置和方法。 双模串行传输装置包括第一和第二电流源，第一和第二反相电路，差分对和电阻串。 第一反相电路接收模式选择信号或第一数据传输信号，第二反相电路接收模式选择信号或第二数据传输信号。 差分对的第一和第二负载端子分别耦合到第一和第二反相电路。 差分对的公共端耦合到第二电流源。 第一和第二差分输入端子接收模式选择信号或分别接收第一和第二数据传输信号。 电阻串串联在第一和第二反相电路的输出端之间。
-
Patent Agency Ranking
4.发明申请公开(公告)号：US20160226557A1
公开(公告)日：2016-08-04
申请号：US14723449
申请日：2015-05-27
Applicant: Novatek Microelectronics Corp.
Inventor： Ren-Hong Luo , Yan-Ting Wang , Hsiang-Chi Li , Mu-Jung Chen
Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.
Abstract translation: 提供了一种用于切换其模式的双模串行传输装置和方法。 双模串行传输装置包括第一和第二电流源，第一和第二反相电路，差分对和电阻串。 第一反相电路接收模式选择信号或第一数据传输信号，第二反相电路接收模式选择信号或第二数据传输信号。 差分对的第一和第二负载端子分别耦合到第一和第二反相电路。 差分对的公共端耦合到第二电流源。 第一和第二差分输入端子接收模式选择信号或分别接收第一和第二数据传输信号。 电阻串串联在第一和第二反相电路的输出端之间。
-
公开(公告)号：US12261610B2
公开(公告)日：2025-03-25
申请号：US18496908
申请日：2023-10-29
Applicant: NOVATEK Microelectronics Corp.
Inventor： Chin-Tung Chan , Yan-Ting Wang , Ren-Hong Luo , Chih-Wen Chen , Hao-Che Hsu , Li-Wei Lin
Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.
-
公开(公告)号：US12009949B2
公开(公告)日：2024-06-11
申请号：US17501985
申请日：2021-10-14
Applicant: Novatek Microelectronics Corp.
Inventor： Hao-Che Hsu , Chin-Tung Chan , Ying-Cheng Lin , Ren-Hong Luo
CPC classification number: H04L25/0272 , H03F3/45076 , H04L25/028
Abstract: A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.
-
公开(公告)号：US11031936B1
公开(公告)日：2021-06-08
申请号：US16852533
申请日：2020-04-19
Applicant: NOVATEK Microelectronics Corp.
Inventor： Ren-Hong Luo , Kun-Jui Shen , Ying-Cheng Lin
IPC: H03K3/00 , H03K19/0185
Abstract: A hybrid transmitter includes a current-mode driver, a voltage-mode driver and an auxiliary driver. The current-mode driver is configured to perform a current transmission. The voltage-mode driver is configured to perform a voltage transmission. The auxiliary driver, coupled to the current-mode driver and the voltage-mode driver, is configured to cooperate with the current-mode driver to enhance a driving capability of the current transmission and cooperate with the voltage-mode driver to enhance a driving capability of the voltage transmission.
-
公开(公告)号：US09800265B2
公开(公告)日：2017-10-24
申请号：US15409478
申请日：2017-01-18
Applicant: Novatek Microelectronics Corp.
Inventor： Shih-Chun Lin , Ren-Hong Luo , Mu-Jung Chen , Yung-Cheng Lin
CPC classification number: H03M9/00 , H03K3/037 , H03K5/01 , H03K5/15046 , H03K2005/00019
Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.017 seconds)
