公开(公告)号：US11362011B2

公开(公告)日：2022-06-14

申请号：US17486313

申请日：2021-09-27

申请人： NUVOTON TECHNOLOGY CORPORATION JAPAN

发明人： Kazuhiko Ohhashi ,  Masatoshi Kamitani ,  Kouki Yamamoto

IPC分类号： H03F3/195 ,  H01L23/367 ,  H01L23/48 ,  H01L23/66 ,  H03F1/30 ,  H03F3/213

摘要： A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.

公开(公告)号：US12080664B2

公开(公告)日：2024-09-03

申请号：US18477224

申请日：2023-09-28

申请人： Nuvoton Technology Corporation Japan

发明人： Kouki Yamamoto ,  Shinichi Akiyoshi ,  Ryouichi Ajimoto

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L29/78

CPC分类号： H01L24/06 ,  H01L24/08 ,  H01L25/0655 ,  H01L29/7813 ,  H01L2224/06152 ,  H01L2224/08225

摘要： A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.

公开(公告)号：US11894456B2

公开(公告)日：2024-02-06

申请号：US18330053

申请日：2023-06-06

申请人： Nuvoton Technology Corporation Japan

发明人： Kouki Yamamoto ,  Haruhisa Takata

IPC分类号： H01L29/78 ,  H02J7/00 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

CPC分类号： H01L29/7802 ,  H01L27/088 ,  H01L29/41725 ,  H01L29/4232 ,  H02J7/0029

摘要： A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.