公开(公告)号：US12132019B2

公开(公告)日：2024-10-29

申请号：US18151622

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/06182 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/08225 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2224/83099 ,  H01L2224/8389 ,  H01L2224/92142 ,  H01L2225/06541 ,  H01L2225/06548

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US12113490B2

公开(公告)日：2024-10-08

申请号：US18517065

申请日：2023-11-22

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Basim Noori ,  Marvin Marbell ,  Qianli Mu ,  Kwangmo Chris Lim ,  Michael E. Watts ,  Mario Bokatius ,  Jangheon Kim

IPC: H03F3/187 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L29/778 ,  H03F1/56 ,  H03F3/193

CPC classification number: H03F1/565 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/08 ,  H01L29/778 ,  H03F3/193 ,  H01L2224/08225 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

Abstract: RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.

公开(公告)号：US20240332267A1

公开(公告)日：2024-10-03

申请号：US18617086

申请日：2024-03-26

Applicant: Adeia Semiconductor Bonding Technologies, Inc.

Inventor： Belgacem HABA ,  Cyprian Emeka UZOH ,  Rajesh KATKAR

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5286 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/08225

Abstract: In some embodiments, a structure comprises an active element having a frontside and a backside opposite the frontside, the active element having active circuitry nearer the frontside than the backside and a power redistribution element having a frontside hybrid bonded to the backside of the active element, the power redistribution element comprising a first plurality of contact pads on the frontside of the power redistribution element and a second plurality of contact pads on a backside of the power redistribution element opposite the frontside of the power redistribution element, a pitch of the first plurality of contact pads is smaller than a pitch of the second plurality of contact pads, the power redistribution element configured to supply at least one of power and ground to the active element.

公开(公告)号：US20240332256A1

公开(公告)日：2024-10-03

申请号：US18382807

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Young Kun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate including a mounting region and an edge region at least partially surrounding the mounting region, a bridge chip on a top surface of the mounting region of the package substrate, a first connection pad and a second connection pad on the mounting region of the package substrate and spaced apart from the bridge chip, a third connection pad on the edge region of the package substrate, a first mold layer on the package substrate and at least partially surrounding the bridge chip, the first connection pad, the second connection pad and the third connection pad, a first semiconductor chip on the first connection pad and the bridge chip, a second semiconductor chip on the second connection pad and the bridge chip, and a conductive post on the third connection pad.

公开(公告)号：US20240312920A1

公开(公告)日：2024-09-19

申请号：US18374310

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunho CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L24/16 ,  H01L25/18 ,  H10B80/00 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: A semiconductor package includes: a first redistribution structure having a structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip disposed on the first redistribution structure; a second semiconductor chip disposed on the first redistribution structure; and bumps disposed between the first redistribution structure and the first semiconductor chip and between the first redistribution structure and the second semiconductor chip, wherein the at least one first redistribution layer includes a detour redistribution line disposed so that a portion of the detour redistribution line overlaps a space between the first and second semiconductor chips, and the detour redistribution line circuitously extends across the space between the first and second semiconductor chips so as not to overlap a stress concentration region partially overlapping a portion of the space between the first and second semiconductor chips, or extends into the stress concentration region.

公开(公告)号：US20240304575A1

公开(公告)日：2024-09-12

申请号：US18517471

申请日：2023-11-22

Applicant: TONG HSING ELECTRONIC INDUSTRIES, LTD.

Inventor： ZZU-CHI CHIU ,  WEI-CHUNG CHAO ,  YAN-WEI CHEN

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/0311 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/08225 ,  H01L2224/48229 ,  H01L2924/2064

Abstract: A bonding structure for connecting a chip and a metal material, and a manufacturing method thereof are provided. The bonding structure includes a substrate, a chip, a metal member, at least one metal wire and an alloy connection layer. An upper surface of the substrate has a first metal pad and a second metal pad. The chip is disposed on the first metal pad. The metal member is disposed above the chip. The at least one metal wire has a first end and a second end, the first end is connected to an upper surface of the metal piece, and the second end is connected to the second metal pad. The alloy connection layer is connected between the metal member and the chip, and covers at least a part of a lower surface of the metal member.

公开(公告)号：US20240258297A1

公开(公告)日：2024-08-01

申请号：US18409824

申请日：2024-01-11

Applicant: InnoLux Corporation

Inventor： Kuang-Ming FAN ,  Ju-Li Wang ,  Chin-Ming Huang ,  Sheng-Nan Chen

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/08 ,  H01L24/94 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2224/08225 ,  H01L2224/94 ,  H01L2924/181

Abstract: A manufacturing method of an electronic device and an electronic device are disclosed. The method includes: forming an intermediate layer on a first carrier, patterning the intermediate layer to form alignment marks; forming a release layer on the first carrier; disposing chips on the release layer, each chip including a bonding pad and a surface; forming an insulating layer surrounding the chips on the release layer to form a package structure; transferring the package structure to a second carrier, enabling the surface of each chip to face away from the second carrier and to be exposed by an upper surface of the insulating layer, a step difference formed between the surface of each chip and at least a portion of the upper surface of the insulating layer in a normal direction; and forming a redistribution layer electrically connected to each chip through the bonding pads on the package structure.

公开(公告)号：US20240250037A1

公开(公告)日：2024-07-25

申请号：US18416560

申请日：2024-01-18

Applicant: Samsung Display Co., LTD.

Inventor： Gana KIM ,  Jangyeol YOON

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/13 ,  H10K59/82

CPC classification number: H01L23/5387 ,  H01L23/5385 ,  H01L24/08 ,  H01L25/13 ,  H10K59/82 ,  H01L2224/08225

Abstract: A display device includes: a display panel including light-emitting elements, a circuit board, and a flexible film electrically connected to the display panel and the circuit board. The flexible film includes: a first portion in which a plurality of first pads electrically connected to the display panel is arranged, a second portion in which a plurality of second pads electrically connected to the circuit board is arranged, and a third portion between the first portion and the second portion. The first portion defines a first cutout pattern therein and between two first pads adjacent to each other among the plurality of first pads, and the first cutout pattern extends to a first edge of the first portion in the flexible film.

公开(公告)号：US20240250011A1

公开(公告)日：2024-07-25

申请号：US18351975

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongho HONG ,  Hyunseok CHOI

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/16227

Abstract: The present disclosure relates to fan-out semiconductor packages and a methods for manufacturing the same. A fan-out semiconductor package includes a substrate including a cavity, a semiconductor die within the cavity and including a plurality of connection terminals at a bottom surface thereof, a dummy die at a fan-out region within the cavity and including a plurality of through silicon vias (TSVs), a filler filling an empty space within the cavity, and a lower redistribution layer on bottom surfaces of the substrate, the semiconductor die, and the dummy die, and electrically connected to at least some of the plurality of connection terminals of the semiconductor die and the plurality of through silicon vias of the dummy die, and an upper redistribution layer on top surfaces of the substrate, the semiconductor die, and the dummy die, and electrically connected to the plurality of through silicon vias of the dummy die.

公开(公告)号：US20240234375A1

公开(公告)日：2024-07-11

申请号：US18429471

申请日：2024-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Hsien Chiang ,  Hui-Chun Chiang ,  Tzu-Sung Huang ,  Ming-Hung Tseng ,  Kris Lipu Chuang ,  Chung-Ming Weng ,  Tsung-Yuan Yu ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L25/105 ,  H01L25/50 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/02141 ,  H01L2224/0311 ,  H01L2224/0312 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/08225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.