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    USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP
    1.
    发明申请
    USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP 有权

    公开(公告)号：US20250103529A1

    公开(公告)日：2025-03-27

    申请号：US18970570

    申请日：2024-12-05

    Applicant: NVIDIA Corporation

    Inventor： Ahmad Itani ,  Yen-Te Shih ,  Jagadeesh Sankaran ,  Ravi P. Singh ,  Ching-Yu Hung

    IPC: G06F13/28

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    Programmable vision accelerator
    4.
    发明授权
    Programmable vision accelerator 有权

    公开(公告)号：US11630800B2

    公开(公告)日：2023-04-18

    申请号：US15141703

    申请日：2016-04-28

    Applicant: NVIDIA Corporation

    Inventor： Ching Y. Hung ,  Jagadeesh Sankaran ,  Ravi P. Singh ,  Stanley Tzeng

    IPC: G06F9/30 ,  G06F15/82 ,  G06F9/32 ,  G06F9/38 ,  G06F9/345 ,  G06F9/34 ,  G06F12/02 ,  G06F15/80

    Abstract: In one embodiment of the present invention, a programmable vision accelerator enables applications to collapse multi-dimensional loops into one dimensional loops. In general, configurable components included in the programmable vision accelerator work together to facilitate such loop collapsing. The configurable elements include multi-dimensional address generators, vector units, and load/store units. Each multi-dimensional address generator generates a different address pattern. Each address pattern represents an overall addressing sequence associated with an object accessed within the collapsed loop. The vector units and the load store units provide execution functionality typically associated with multi-dimensional loops based on the address pattern. Advantageously, collapsing multi-dimensional loops in a flexible manner dramatically reduces the overhead associated with implementing a wide range of computer vision algorithms. Consequently, the overall performance of many computer vision applications may be optimized.

    SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A SYSTEM ON A CHIP
    5.
    发明申请
    SIMD DATA PATH ORGANIZATION TO INCREASE PROCESSING THROUGHPUT IN A SYSTEM ON A CHIP 有权

    公开(公告)号：US20230050062A1

    公开(公告)日：2023-02-16

    申请号：US17391395

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ching-Yu Hung ,  Ravi P. Singh ,  Jagadeesh Sankaran ,  Yen-Te Shih ,  Ahmad Itani

    IPC: G06F9/30 ,  G06F9/38

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP
    6.
    发明申请
    USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP 有权

    公开(公告)号：US20230048836A1

    公开(公告)日：2023-02-16

    申请号：US17391875

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ahmad Itani ,  Yen-Te Shih ,  Jagadeesh Sankaran ,  Ravi P Singh ,  Ching-Yu Hung

    IPC: G06F9/30 ,  G06F15/80 ,  G06F13/28

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP
    7.
    发明申请
    USING A HARDWARE SEQUENCER IN A DIRECT MEMORY ACCESS SYSTEM OF A SYSTEM ON A CHIP 有权

    公开(公告)号：US20230042226A1

    公开(公告)日：2023-02-09

    申请号：US17391867

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ahmad Itani ,  Yen-Te Shih ,  Jagadeesh Sankaran ,  Ravi P. Singh ,  Ching-Yu Hung

    IPC: G06F13/28

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    Using a hardware sequencer in a direct memory access system of a system on a chip
    8.
    发明授权
    Using a hardware sequencer in a direct memory access system of a system on a chip 有权

    公开(公告)号：US12204475B2

    公开(公告)日：2025-01-21

    申请号：US18064121

    申请日：2022-12-09

    Applicant: NVIDIA Corporation

    Inventor： Ahmad Itani ,  Yen-Te Shih ,  Jagadeesh Sankaran ,  Ravi P Singh ,  Ching-Yu Hung

    IPC: G06F13/28

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

    Performing load and permute with a single instruction in a system on a chip
    9.
    发明授权
    Performing load and permute with a single instruction in a system on a chip 有权

    公开(公告)号：US12118353B2

    公开(公告)日：2024-10-15

    申请号：US17391491

    申请日：2021-08-02

    Applicant: NVIDIA Corporation

    Inventor： Ching-Yu Hung ,  Ravi P Singh ,  Jagadeesh Sankaran ,  Yen-Te Shih ,  Ahmad Itani

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30036 ,  G06F9/30101 ,  G06F9/3887

    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

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