公开(公告)号：US10078911B2

公开(公告)日：2018-09-18

申请号：US13843981

申请日：2013-03-15

Applicant: NVIDIA Corporation

Inventor： Ziyad Sami Hakura ,  Yury Uralsky ,  Tyson Bergland ,  Eric Brian Lum ,  Jerome F. Duluk ,  Henry Packard Moreton

IPC: G09G5/14 ,  G06T15/00 ,  H04N13/00

CPC classification number: G06T15/005 ,  G09G5/14 ,  H04N13/128 ,  H04N2013/0081

Abstract: A system, method, and computer program product are provided for executing processes involving at least one primitive in a graphics processor, utilizing a data structure. In operation, a data structure is associated with at least one primitive. Additionally, a plurality of processes involving the at least one primitive are executed in a graphics processor, utilizing the data structure. Moreover, the plurality of processes include at least one of selecting at least one surface or portion thereof to which to render, or selecting at least one of a plurality of viewports.

公开(公告)号：US10915364B2

公开(公告)日：2021-02-09

申请号：US15368434

申请日：2016-12-02

Applicant: Nvidia Corporation

Inventor： Stephen Jones ,  Philip Alexander Cuadra ,  Daniel Elliot Wexler ,  Ignacio Llamas ,  Lacky V. Shah ,  Jerome F. Duluk ,  Christopher Lamb

IPC: G06F9/46 ,  G06F9/50 ,  G06T1/20 ,  G06F9/52

Abstract: Apparatuses, systems, and techniques for performing nested kernel execution within a parallel processing subsystem. In at least one embodiment, a parent thread launches a nested child grid on the parallel processing subsystem, and enables the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid.

公开(公告)号：US20170083373A1

公开(公告)日：2017-03-23

申请号：US15368434

申请日：2016-12-02

Applicant: Nvidia Corporation

Inventor： Stephen Jones ,  Philip Alexander Cuadra ,  Daniel Elliot Wexler ,  Ignacio Llamas ,  Lacky V. Shah ,  Jerome F. Duluk ,  Christopher Lamb

IPC: G06F9/50 ,  G06T1/20 ,  G06F9/52

CPC classification number: G06F9/5027 ,  G06F9/522 ,  G06F2209/483 ,  G06T1/20

Abstract: One embodiment of the present invention sets forth a technique for performing nested kernel execution within a parallel processing subsystem. The technique involves enabling a parent thread to launch a nested child grid on the parallel processing subsystem, and enabling the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid. This technique advantageously enables the parallel processing subsystem to perform a richer set of programming constructs, such as conditionally executed and nested operations and externally defined library functions without the additional complexity of CPU involvement.

公开(公告)号：US20140176568A1

公开(公告)日：2014-06-26

申请号：US13723092

申请日：2012-12-20

Applicant: NVIDIA CORPORATION

Inventor： Rui BASTOS ,  Mark J. Kilgard ,  William Craig McKnight ,  Jerome F. Duluk ,  Pierre Souillot ,  Dale L. Kirkland ,  Christian Amsinck ,  Joseph Detmer ,  Christian Rouet ,  Don Bittel

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/503 ,  G09G2340/10

Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.

Abstract translation: 用于有效地呈现内容的技术将每个复合混合模式减少到一系列基本的混合操作。 一系列基本混合操作在循环管线内执行，直到计算最终混合值。 再循环管线位于图形处理单元的彩色光栅操作单元内，用于有效地访问图像缓冲器数据。