公开(公告)号：US20230070125A1

公开(公告)日：2023-03-09

申请号：US17467718

申请日：2021-09-07

Applicant: NVIDIA Corporation

Inventor： Jonathon Evans ,  Kaushal Agarwal

IPC: G06F21/79 ,  H04L9/32 ,  G06F12/1045 ,  G06F12/14

Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may incorporate the physical address and a signature of the physical address generated using a private key into a translated address field of a response to a translation request. An endpoint may treat the combination as a translated address by storing it in an entry of a translation cache, and accessing the entry for inclusion in a memory access request. The host may generate a signature of the translated address from the request using the private key, with the result being compared to the signature from the request. The memory access request may be verified when the compared values match, and the memory access may be performed using the translated address.

公开(公告)号：US20210191754A1

公开(公告)日：2021-06-24

申请号：US16722422

申请日：2019-12-20

Applicant: Nvidia Corporation

Inventor： Jonathon Evans ,  Lacky Shah ,  Phil Johnson ,  Jonah Alben ,  Brian Pharris ,  Greg Palmer ,  Brian Fahs

IPC: G06F9/48 ,  G06N3/08

Abstract: Apparatuses, systems, and techniques to optimize processor resources at a user-defined level. In at least one embodiment, priority of one or more tasks are adjusted to prevent one or more other dependent tasks from entering an idle state due to lack of resources to consume.

公开(公告)号：US10430356B2

公开(公告)日：2019-10-01

申请号：US15582459

申请日：2017-04-28

Applicant: NVIDIA Corporation

Inventor： M. Wasiur Rashid ,  Jonathon Evans ,  Gary Ward ,  Philip Browning Johnson

IPC: G06F3/06 ,  G06F13/28 ,  G06F12/109 ,  G06F13/40

Abstract: Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.

公开(公告)号：US11954518B2

公开(公告)日：2024-04-09

申请号：US16722422

申请日：2019-12-20

Applicant: Nvidia Corporation

Inventor： Jonathon Evans ,  Lacky Shah ,  Phil Johnson ,  Jonah Alben ,  Brian Pharris ,  Greg Palmer ,  Brian Fahs

IPC: G06F9/48 ,  G06N3/08

CPC classification number: G06F9/4831 ,  G06N3/08

Abstract: Apparatuses, systems, and techniques to optimize processor resources at a user-defined level. In at least one embodiment, priority of one or more tasks are adjusted to prevent one or more other dependent tasks from entering an idle state due to lack of resources to consume.

公开(公告)号：US11934567B2

公开(公告)日：2024-03-19

申请号：US17467718

申请日：2021-09-07

Applicant: NVIDIA Corporation

Inventor： Jonathon Evans ,  Kaushal Agarwal

IPC: G06F21/79 ,  G06F12/1045 ,  G06F12/14 ,  H04L9/32

CPC classification number: G06F21/79 ,  G06F12/1054 ,  G06F12/1063 ,  G06F12/1408 ,  H04L9/3247 ,  G06F2212/1052 ,  G06F2212/657

Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may incorporate the physical address and a signature of the physical address generated using a private key into a translated address field of a response to a translation request. An endpoint may treat the combination as a translated address by storing it in an entry of a translation cache, and accessing the entry for inclusion in a memory access request. The host may generate a signature of the translated address from the request using the private key, with the result being compared to the signature from the request. The memory access request may be verified when the compared values match, and the memory access may be performed using the translated address.

公开(公告)号：US20230259464A1

公开(公告)日：2023-08-17

申请号：US17671144

申请日：2022-02-14

Applicant: NVIDIA Corporation

Inventor： Jonathon Evans

IPC: G06F12/14

CPC classification number: G06F12/1483 ,  G06F2212/1052 ,  G06F2212/657

Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may record permissions granting entities access to physical addresses in physical address access permissions tables (PAAPTs) responsive to the address translation. The security of address translation services may be increased based at least on verifying memory access requests are authorized using the PAAPTs. For example, an entity identifier included in a request may be used to locate a corresponding PAAPT, and a physical address may be extracted from the request and used to locate an entry indicating whether an entity corresponding to the entity identifier has permission to access the physical address. Where the entity has permission, the system may perform the memory access using the physical address. Otherwise an error or fault code may be provided in response to the request.