公开(公告)号：US10175715B2

公开(公告)日：2019-01-08

申请号：US15272145

申请日：2016-09-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Charles Qingle Wu ,  Li Yang ,  Zhenhua Zhu

IPC: G06F3/00 ,  G06F13/42 ,  G06F1/08 ,  H04N5/374

Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.

公开(公告)号：US20180081389A1

公开(公告)日：2018-03-22

申请号：US15272145

申请日：2016-09-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Charles Qingle Wu ,  Li Yang ,  Zhenhua Zhu

IPC: G06F1/08 ,  G06F13/42

CPC classification number: G06F1/08 ,  G06F3/005 ,  G06F13/4291 ,  H04N5/374

Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.