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    POST-SILICON REPAIR OF ON-DIE NETWORKS
    2.
    发明申请
    POST-SILICON REPAIR OF ON-DIE NETWORKS 有权
    电脑网络后硅修复

    公开(公告)号：US20140140205A1

    公开(公告)日：2014-05-22

    申请号：US13681052

    申请日：2012-11-19

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Robert P. Masleid ,  Paul J. Dickinson ,  Murali M. R. Gala ,  Karl P. Dahlgren

    IPC: H04L29/14

    CPC classification number: H04L29/14 ,  H04L49/109 ,  H04L49/557

    Abstract: A method and apparatus for post-silicon repair of on-die networks is disclosed. In one embodiment, an integrated circuit includes a first network node of an on-chip network configured to couple each of a plurality of functional units to at least one other one of the plurality of functional units. The first network node includes a plurality of ports. Each of the plurality of ports includes a plurality of multiplexers configured to substitute a spare channel of the network node into the network responsive to a test determining that another one of a plurality of channels is defective.

    Abstract translation: 公开了一种用于片上网络后硅修复的方法和装置。 在一个实施例中，集成电路包括片上网络的第一网络节点，其被配置为将多个功能单元中的每一个耦合到所述多个功能单元中的至少另一个功能单元。 第一网络节点包括多个端口。 多个端口中的每一个包括多个复用器，其被配置为响应于确定多个信道中的另一个是有缺陷的测试来将网络节点的备用信道替换到网络中。

    At-Speed Test of Memory Arrays Using Scan
    3.
    发明申请
    At-Speed Test of Memory Arrays Using Scan 有权
    使用扫描的内存阵列的速度测试

    公开(公告)号：US20150325314A1

    公开(公告)日：2015-11-12

    申请号：US14273851

    申请日：2014-05-09

    Applicant: Oracle International Corporation

    Inventor： Thomas A Ziaja ,  Murali M. R. Gala

    IPC: G11C29/12 ,  G11C7/10

    CPC classification number: G11C29/32 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/3187 ,  G06F11/27 ,  G11C7/1036 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C29/12 ,  G11C29/12015 ,  G11C2207/007

    Abstract: A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.

    Abstract translation: 公开了一种用于对集成电路（IC）中的存储器阵列进行高速测试的方法和装置。 在一个实施例中，IC包括存储器阵列和耦合以将输入信号提供到存储器阵列中的多个输入电路。 多个输入电路中的每一个包括具有耦合到存储器阵列的对应输入的数据输出的输入触发器，选择电路被配置为选择到输入触发器的数据输入的数据路径和数据路径移位 寄存器耦合以控制提供给选择电路的选择信号的状态，其中数据路径移位寄存器包括多个多路复用器。 当在测试模式下操作IC时，多个输入电路被配置为以IC的工作时钟速度向存储器阵列提供输入信号。

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