SHIFT REGISTER CIRCUITRY AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUITRY AND DISPLAY DEVICE

    公开(公告)号:US20190080780A1

    公开(公告)日:2019-03-14

    申请号:US15772410

    申请日:2017-10-30

    IPC分类号: G11C19/28 G09G3/20

    摘要: Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.

    SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS
    3.
    发明申请
    SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS 审中-公开
    移动寄存器及其驱动方法,门驱动电路和显示设备

    公开(公告)号:US20170061922A1

    公开(公告)日:2017-03-02

    申请号:US15145269

    申请日:2016-05-03

    发明人: Jiguo WANG

    IPC分类号: G09G5/00 G11C19/28

    摘要: There are presented a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register includes a first feedback module and a pull-down module, wherein the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register. The shift register is used to enhance noise resistance capability of the shift register.

    摘要翻译: 提出了移位寄存器及其驱动方法,门驱动电路和显示装置。 移位寄存器包括第一反馈模块和下拉模块,其中第一反馈模块包括至少两个反馈单元,各个反馈单元的控制端分别连接到不同的控制点,每个反馈单元的输入端连接到 第一级输入端子和连接到第一节点的输出端子,第一节点连接到下拉模块的控制端子,并且下拉模块具有连接到第一级输入端子的输入端子和 输出端子连接到移位寄存器的信号输出端子。 移位寄存器用于增强移位寄存器的抗噪声能力。

    SHIFT REGISTER, GOA CIRCUIT, DISPLAY DEVICE AND DRIVING METHOD

    公开(公告)号:US20200258464A1

    公开(公告)日:2020-08-13

    申请号:US15769036

    申请日:2017-10-10

    发明人: Jiguo WANG

    IPC分类号: G09G3/36 H04M1/02 G11C19/28

    摘要: The present disclosure provides a shift register, a GOA circuit, a display device, and a driving method. A shift register is provided which comprises: at least one input sub-circuit for charging a pull-up node; at least one output sub-circuit for outputting a respective clock signal; first reset sub-circuit(s) for pulling the potential of the respective signal output terminal down to a reference potential; a first noise reduction sub-circuit for performing noise reduction on the pull-up node through a signal input from the reference potential terminal; a second noise reduction sub-circuit for performing noise reduction on the pull-down node through a signal input from the reference potential terminal; and a second reset sub-circuit for controlling the potential of the pull-down node under control of a signal input from the reset clock signal input terminal.

    PIXEL CIRCUIT AND DRIVING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

    公开(公告)号:US20210074231A1

    公开(公告)日:2021-03-11

    申请号:US16959372

    申请日:2019-12-23

    发明人: Jiguo WANG Jun FAN

    IPC分类号: G09G3/36 G09G3/20

    摘要: The present disclosure provides a pixel circuit and a driving method thereof, a display panel and a display device. The pixel circuit includes a switching circuit, an inverter, a potential maintaining circuit, and a charging circuit, the switching circuit writes data voltage signal into a first node under control of scanning signal, the first node is connection node of the switching circuit, the inverter, the potential maintaining circuit and the charging circuit; the inverter inverts potential of the first node and outputs inverted potential to a second node, the second node is connection node of the inverter and the charging circuit; the potential maintaining circuit maintains potential of the first node in response to the switching circuit being turned off; and the charging circuit controls display of a display unit according to potential of the first node and potential of the second node.

    SHIFT REGISTER AND CORRESPONDING DRIVING METHOD, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

    公开(公告)号:US20200286570A1

    公开(公告)日:2020-09-10

    申请号:US16339752

    申请日:2018-09-14

    IPC分类号: G11C19/28 G09G3/20

    摘要: A shift register and a corresponding driving method, a gate driving circuit and a display device, the shift registers includes an input and reset circuit, a first output circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit; the first output circuit and the second output circuit output gate driving signals according to potentials at a first clock signal terminal and a second clock signal terminal respectively, the first pull-down circuit and the second pull-down circuit reset potentials at a pull up node, a first output terminal a second output terminal according to potentials at a first pull-down node a second pull-down node respectively.

    GATE DRIVING SUB-CIRCUIT, DRIVING METHOD AND GATE DRIVING CIRCUIT

    公开(公告)号:US20200160769A1

    公开(公告)日:2020-05-21

    申请号:US16622756

    申请日:2018-11-12

    IPC分类号: G09G3/20 G11C19/28

    摘要: A gate driving sub-circuit, a driving method and a gate driving circuit are provided. The gate driving sub-circuit includes an input signal end, a shift signal output end, an inverted phase shift signal output end, a positive phase shift clock signal input end, an inverted phase shift clock signal input end, a first control clock signal input end, a second control clock signal input end, a first gate driving signal output end, a second gate driving signal output end, a shift register circuit and a control output circuit. The control output circuit includes a first control output sub-circuit and a second control output sub-circuit.