摘要:
A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.
摘要:
A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.
摘要:
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.
摘要:
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.
摘要:
In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.
摘要:
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.
摘要:
Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual block boundaries with the reduced physical data. Some embodiments further merge the post-optimization data back into the original data while reducing logic and physical disturbance to existing designs. Some embodiments anchor driver instance(s) that correspond to excluded side instance(s) or side path(s) to ensure LEC cleanliness and may further trim timing graph(s) based at least on the partial netlist. Some embodiments account for parasitics without static parasitic files. Various embodiments apply to both hierarchical and non-hierarchical designs.
摘要:
A system and method for determining the criticality of each timing pin in a circuit design are disclosed. The criticality of a timing pin is the probability that the timing pin is on the path with the worst slack in the circuit design. According to the methodology, the slack for each timing pin is calculated, wherein each slack is a function of a process random variable. Then, the criticality of each timing pin is determined as the probability of the timing pin having the minimum slack among the slacks in an independent critical set of timing pins. The criticality of each timing pin may then be normalized. By determining the criticalities of the timing pins in a circuit design, a circuit design system may be able to more easily identify portions of the circuit design that need modification for timing and other purposes.
摘要:
A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock ports, creating launch and capture clocks, making exclusive clock groups of the launch clock and the capture clock for opposing clock ports to avoid the launch and capture clocks for each port affecting other internal data paths within the partition block, and associating common path pessimism removal information with a source latency of the capture clock to adjust timing at an end point of the internal data path.
摘要:
A modeling method to improve the accuracy of timing analysis that more closely models timing information associated with layout parasitics that are connected to interface pins of a transistor-level subcircuit. A method is described for performing a hierarchical timing analysis of a circuit having a transistor-level subcircuit. Certain data (e.g., the layout parasitic data associated with interface nodes) associated with the transistor-level subcircuit are set aside. A timing model (timing arcs) of the transistor-level subcircuit is created without using these data. The timing analysis of the circuit is performed using a circuit analyzer. The circuit analyzer uses the timing model (timing arcs) and the layout parasitic data for the transistor-level subcircuit in the timing analysis. Thus, the layout parasitic data associated with the lower level subcircuit is preserved and used in the higher level circuit timing analysis to provide an accurate non-linear timing analysis of the layout parasitics.