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    Semiconductor device comprising eFUSES of enhanced programming efficiency
    1.
    发明授权
    Semiconductor device comprising eFUSES of enhanced programming efficiency 有权
    包括具有增强的编程效率的eFUSES的半导体器件

    公开(公告)号：US08268679B2

    公开(公告)日：2012-09-18

    申请号：US12579654

    申请日：2009-10-15

    申请人： Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

    发明人： Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

    IPC分类号： H01L21/732

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49107 ,  H01L2924/00

    摘要： In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

    摘要翻译： 在复杂的集成电路中，可以形成电子熔断器，使得可以通过包括增加的电流密度的至少一个区域来实现对电迁移的增加的灵敏度。 这可以通过形成相应的熔丝区域作为非线性配置来实现，其中在对应的线性段的连接部分期间，在施加编程电压期间可能发生所需的增强的电流拥挤。 因此，可以实现电子熔断器的增加的可靠性和更节省空间的布局。

    SEMICONDUCTOR DEVICE COMPRISING eFUSES OF ENHANCED PROGRAMMING EFFICIENCY
    2.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING eFUSES OF ENHANCED PROGRAMMING EFFICIENCY 有权
    包含增强编程效率的图像的半导体器件

    公开(公告)号：US20100107403A1

    公开(公告)日：2010-05-06

    申请号：US12579654

    申请日：2009-10-15

    申请人： Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

    发明人： Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

    IPC分类号： H01H69/02

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49107 ,  H01L2924/00

    摘要： In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

    摘要翻译： 在复杂的集成电路中，可以形成电子熔断器，使得可以通过包括增加的电流密度的至少一个区域来实现对电迁移的增加的灵敏度。 这可以通过形成相应的熔丝区域作为非线性配置来实现，其中在对应的线性段的连接部分期间，在施加编程电压期间可能发生所需的增强的电流拥挤。 因此，可以实现电子熔断器的增加的可靠性和更节省空间的布局。

    SEMICONDUCTOR DEVICE COMPRISING A BURIED POLY RESISTOR
    6.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING A BURIED POLY RESISTOR 有权
    包含一个多层聚电阻的半导体器件

    公开(公告)号：US20100078645A1

    公开(公告)日：2010-04-01

    申请号：US12553475

    申请日：2009-09-03

    申请人： Andreas Kurz ,  Roman Boschke ,  James Buller ,  Andy Wei

    发明人： Andreas Kurz ,  Roman Boschke ,  James Buller ,  Andy Wei

    IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L27/06

    CPC分类号： H01L27/0629 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/20

    摘要： An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.

    摘要翻译： 嵌入或埋入的电阻结构可以通过半导体材料的非晶化并随后在多晶态中重新结晶而形成，从而提供与诸如多晶硅电阻器的常规多晶电阻器的高度兼容性，同时避免专用 多晶材料。 因此，多晶电阻器可以有利地与基于非硅栅电极材料的复杂晶体管架构组合，同时还提供相对于寄生电容的电阻器的高性能。

    SOI device with a buried insulating material having increased etch resistivity
    7.
    发明授权
    SOI device with a buried insulating material having increased etch resistivity 有权
    具有掩埋绝缘材料的SOI器件具有增加的蚀刻电阻率

    公开(公告)号：US08617940B2

    公开(公告)日：2013-12-31

    申请号：US12639515

    申请日：2009-12-16

    申请人： Andreas Kurz ,  Roman Boschke ,  Christoph Schwan ,  John Morgan

    发明人： Andreas Kurz ,  Roman Boschke ,  Christoph Schwan ,  John Morgan

    IPC分类号： H01L29/66

    CPC分类号： H01L27/0629 ,  H01L21/31111 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203

    摘要： In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

    摘要翻译： 在SOI器件中，电路元件（例如衬底二极管）的PN结基于掩埋绝缘材料形成在衬底材料中，该掩埋绝缘材料在湿化学清洗和蚀刻工艺期间提供增加的蚀刻电阻率。 因此，可以避免在掩埋绝缘材料的侧壁附近形成的PN结的过度曝光，这可能导致包括二氧化硅材料作为掩埋绝缘层的常规SOI器件的可靠性问题。

    SOI DEVICE WITH A BURIED INSULATING MATERIAL HAVING INCREASED ETCH RESISTIVITY
    9.
    发明申请
    SOI DEVICE WITH A BURIED INSULATING MATERIAL HAVING INCREASED ETCH RESISTIVITY 有权
    具有增加的蚀刻电阻率的绝缘绝缘材料的SOI器件

    公开(公告)号：US20100163994A1

    公开(公告)日：2010-07-01

    申请号：US12639515

    申请日：2009-12-16

    申请人： Andreas Kurz ,  Roman Boschke ,  Christoph Schwan ,  John Morgan

    发明人： Andreas Kurz ,  Roman Boschke ,  Christoph Schwan ,  John Morgan

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L27/0629 ,  H01L21/31111 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203

    摘要： In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

    摘要翻译： 在SOI器件中，电路元件（例如衬底二极管）的PN结基于掩埋绝缘材料形成在衬底材料中，该掩埋绝缘材料在湿化学清洗和蚀刻工艺期间提供增加的蚀刻电阻率。 因此，可以避免在掩埋绝缘材料的侧壁附近形成的PN结的过度曝光，这可能导致包括二氧化硅材料作为掩埋绝缘层的常规SOI器件的可靠性问题。

    Semiconductor device comprising a buried poly resistor
    10.
    发明授权
    Semiconductor device comprising a buried poly resistor 有权
    半导体器件包括埋入的多晶硅电阻器

    公开(公告)号：US08962420B2

    公开(公告)日：2015-02-24

    申请号：US12553475

    申请日：2009-09-03

    申请人： Andreas Kurz ,  Roman Boschke ,  James Buller ,  Andy Wei

    发明人： Andreas Kurz ,  Roman Boschke ,  James Buller ,  Andy Wei

    IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L27/06 ,  H01L21/84 ,  H01L27/12 ,  H01L49/02

    CPC分类号： H01L27/0629 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/20

    摘要： An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.

    摘要翻译： 嵌入或埋入的电阻结构可以通过半导体材料的非晶化并随后在多晶态中重新结晶而形成，从而提供与诸如多晶硅电阻器的常规多晶电阻器的高度兼容性，同时避免专用 多晶材料。 因此，多晶电阻器可以有利地与基于非硅栅电极材料的复杂晶体管架构组合，同时还提供相对于寄生电容的电阻器的高性能。