公开(公告)号：US08314625B2

公开(公告)日：2012-11-20

申请号：US12620664

申请日：2009-11-18

Applicant: Oliver Aubel ,  Frank Feustel ,  Torsten Schmidt

Inventor： Oliver Aubel ,  Frank Feustel ,  Torsten Schmidt

IPC: G01R31/3187 ,  G01R31/26

CPC classification number: H01L22/34

Abstract: In a test structure for determining dielectric breakdown events of a metallization system of semiconductor devices, a built-in compliance functionality may allow reliable switching off of the test voltage prior to causing high leakage currents, which may conventionally result in significant damage. Consequently, further failure analysis may be possible after the occurrence of a dielectric breakdown event.

Abstract translation: 在用于确定半导体器件的金属化系统的绝缘击穿事件的测试结构中，内置的兼容性功能可以允许在引起高泄漏电流之前可靠地关断测试电压，这可能常常导致显着的损坏。 因此，在电介质击穿事件发生之后，进一步的故障分析可能是可能的。

公开(公告)号：US08174010B2

公开(公告)日：2012-05-08

申请号：US11949993

申请日：2007-12-04

Applicant: Frank Feustel ,  Pascal Limbecker ,  Oliver Aubel

Inventor： Frank Feustel ,  Pascal Limbecker ,  Oliver Aubel

IPC: H01L23/58 ,  H01L29/10

CPC classification number: H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration.

Abstract translation: 一种统一的测试结构，其适用于包括具有第一半链和第二半链的电流路径链的半导体器件的所有级别，其中每个半链包括下金属化段，上金属化段，下金属化层之间的绝缘层 段和上部金属化段，以及连接段。 每个连接段电连接到下部金属化段之一的接触区域和上部金属化段之一的接触区域，从而电连接相应的下部金属化段和相应的上部金属化段，并且第一 半链和第二半链具有不同的配置。

公开(公告)号：US07512506B2

公开(公告)日：2009-03-31

申请号：US11755827

申请日：2007-05-31

Applicant: Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

Inventor： Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

IPC: G06F19/00 ,  G01R31/26

CPC classification number: G01R31/2858 ,  G01R31/2875 ,  G01R31/2879

Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.

Abstract translation: 公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。 该方法的一个实施例包括：对线路施加恒定电流Is; 并且在施加恒定电流Is的同时对线进行应力测试，使得恒定电流Is不会由于电迁移开始时的电阻变化而改变。

公开(公告)号：US20080265247A1

公开(公告)日：2008-10-30

申请号：US11949993

申请日：2007-12-04

Applicant: Frank Feustel ,  Pascal Limbecker ,  Oliver Aubel

Inventor： Frank Feustel ,  Pascal Limbecker ,  Oliver Aubel

IPC: H01L23/58

CPC classification number: H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration.

Abstract translation: 一种统一的测试结构，其适用于包括具有第一半链和第二半链的电流路径链的半导体器件的所有级别，其中每个半链包括下金属化段，上金属化段，下金属化层之间的绝缘层 段和上部金属化段，以及连接段。 每个连接段电连接到下部金属化段之一的接触区域和上部金属化段之一的接触区域，从而电连接相应的下部金属化段和相应的上部金属化段，并且第一 半链和第二半链具有不同的配置。

公开(公告)号：US20100107403A1

公开(公告)日：2010-05-06

申请号：US12579654

申请日：2009-10-15

Applicant: Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

Inventor： Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

IPC: H01H69/02

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49107 ,  H01L2924/00

Abstract: In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

Abstract translation: 在复杂的集成电路中，可以形成电子熔断器，使得可以通过包括增加的电流密度的至少一个区域来实现对电迁移的增加的灵敏度。 这可以通过形成相应的熔丝区域作为非线性配置来实现，其中在对应的线性段的连接部分期间，在施加编程电压期间可能发生所需的增强的电流拥挤。 因此，可以实现电子熔断器的增加的可靠性和更节省空间的布局。

公开(公告)号：US20070105366A1

公开(公告)日：2007-05-10

申请号：US11589349

申请日：2006-10-30

Applicant: Oliver Aubel ,  Wolfgang Hasse ,  Martina Hommel ,  Heinrich Koerner

Inventor： Oliver Aubel ,  Wolfgang Hasse ,  Martina Hommel ,  Heinrich Koerner

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76864 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.

Abstract translation: 特别地说明了通过长期热处理在通孔底部或通孔顶部区域去除阻挡材料的方法。 同时或替代地，互连通过长期热处理以简单且不复杂的方式涂覆有阻挡材料。

公开(公告)号：US08643183B2

公开(公告)日：2014-02-04

申请号：US11589349

申请日：2006-10-30

Applicant: Oliver Aubel ,  Wolfgang Hasse ,  Martina Hommel ,  Heinrich Koerner

Inventor： Oliver Aubel ,  Wolfgang Hasse ,  Martina Hommel ,  Heinrich Koerner

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76864 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.

Abstract translation: 特别地说明了通过长期热处理在通孔底部或通孔顶部区域去除阻挡材料的方法。 同时或替代地，互连通过长期热处理以简单且不复杂的方式涂覆有阻挡材料。

公开(公告)号：US08268679B2

公开(公告)日：2012-09-18

申请号：US12579654

申请日：2009-10-15

Applicant: Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

Inventor： Oliver Aubel ,  Jens Poppe ,  Andreas Kurz ,  Roman Boschke

IPC: H01L21/732

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49107 ,  H01L2924/00

Abstract: In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

Abstract translation: 在复杂的集成电路中，可以形成电子熔断器，使得可以通过包括增加的电流密度的至少一个区域来实现对电迁移的增加的灵敏度。 这可以通过形成相应的熔丝区域作为非线性配置来实现，其中在对应的线性段的连接部分期间，在施加编程电压期间可能发生所需的增强的电流拥挤。 因此，可以实现电子熔断器的增加的可靠性和更节省空间的布局。

公开(公告)号：US20080297188A1

公开(公告)日：2008-12-04

申请号：US11755827

申请日：2007-05-31

Applicant: Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

Inventor： Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  G01R31/2875 ,  G01R31/2879

Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.

Abstract translation: 公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。 该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

公开(公告)号：US20120153479A1

公开(公告)日：2012-06-21

申请号：US13190214

申请日：2011-07-25

Applicant: Oliver Aubel ,  Christian Hennesthal ,  Frank Feustel ,  Thomas Werner

Inventor： Oliver Aubel ,  Christian Hennesthal ,  Frank Feustel ,  Thomas Werner

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76847 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In metallization systems of complex semiconductor devices, an intermediate interface layer may be incorporated into the interconnect structures in order to provide superior electromigration performance. To this end, the deposition of the actual fill material may be interrupted at an appropriate stage and the interface layer may be formed, for instance, by deposition, surface treatment and the like, followed by the further deposition of the actual fill metal. In this manner, the grain size issue, in particular at lower portions of the scaled inter-connect features, may be addressed.

Abstract translation: 在复杂半导体器件的金属化系统中，中间接口层可以并入到互连结构中，以便提供优异的电迁移性能。 为此，实际填充材料的沉积可以在适当的阶段被中断，并且界面层可以例如通过沉积，表面处理等形成，然后进一步沉积实际的填充金属。 以这种方式，可以解决晶粒尺寸问题，特别是在缩放的互连特征的较低部分。