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公开(公告)号：US6147566A
公开(公告)日：2000-11-14
申请号：US995667
申请日：1997-12-22
CPC分类号： H02M3/073 , H03K3/0315
摘要： An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals. First and second RC type circuits produce the first and second driving signals to control the transitions in the third and fourth logic signals. The oscillator circuit can be used in a switch-over control circuit for a load pump type of high-voltage generator.
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2.发明授权Electronic structure comprising high and low voltage transistors, and a corresponding fabrication method 有权包括高压和低压晶体管的电子结构及相应的制造方法公开(公告)号：US06268633B1
公开(公告)日：2001-07-31
申请号：US09222568
申请日：1998-12-28
申请人： Federico Pio , Olivier Pizzuto
发明人： Federico Pio , Olivier Pizzuto
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.
摘要翻译： 集成在具有第一类型导电性的半导体衬底中的电子器件的结构，其包括至少第一HV晶体管和至少第二LV晶体管，每个具有相应的栅极区域。 所述第一HV晶体管具有具有第二类型导电性的轻掺杂漏极和源极区，并且所述第二LV晶体管具有具有第二类型导电性的各自的漏极和源极区，每个包含与相应栅极区相邻的轻掺杂部分， 第二部分是更重掺杂的并且包括硅化物层。
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3.发明授权公开(公告)号：US07183160B2
公开(公告)日：2007-02-27
申请号：US10763044
申请日：2004-01-22
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： The invention relates to a production process for a flash memory from a semi-conductor substrate fitted with at least two adjacent rows of precursor stacks of floating gate transistors, the precursor stacks being at least partially covered by a protective resin and being separated by a formation zone for a source line. The process includes forming a trench in the formation zone for the source line by an attack of this zone and of the protective resin. The result of the attack step includes a deposit of residue from the resin below the precursor stacks. The residue deposit is removed. A source line is implanted in the formation zone below the precursor stacks. This process enables the time needed for erasing the memory to be reduced.
摘要翻译： 本发明涉及一种用于从半导体衬底制造的闪存的制造方法，所述半导体衬底装配有至少两排相邻的浮动栅极晶体管的前驱叠层，所述前体叠层至少部分地被保护树脂覆盖并由地层 源线的区域。 该方法包括通过该区域和保护树脂的攻击在源极线的形成区域中形成沟槽。 攻击步骤的结果包括从前体堆叠下面的树脂沉积残留物。 残留物沉积物被去除。 将源极线植入在前体叠层下方的形成区域中。 该过程使得能够减少擦除存储器所需的时间。
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4.发明申请公开(公告)号：US20050087816A1
公开(公告)日：2005-04-28
申请号：US10763044
申请日：2004-01-22
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L21/82 , H01L29/94
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： The invention relates to a production process for a flash memory from a semi-conductor substrate fitted with at least two adjacent rows of precursor stacks of floating gate transistors, the precursor stacks being at least partially covered by a protective resin and being separated by a formation zone for a source line. The process includes forming a trench in the formation zone for the source line by an attack of this zone and of the protective resin. The result of the attack step includes a deposit of residue from the resin below the precursor stacks. The residue deposit is removed. A source line is implanted in the formation zone below the precursor stacks. This process enables the time needed for erasing the memory to be reduced.
摘要翻译： 本发明涉及一种用于从半导体衬底制造的闪存的制造方法，所述半导体衬底装配有至少两排相邻的浮动栅极晶体管的前驱叠层，所述前体叠层至少部分地被保护树脂覆盖并由地层 源线的区域。 该方法包括通过该区域和保护树脂的攻击在源极线的形成区域中形成沟槽。 攻击步骤的结果包括从前体堆叠下面的树脂沉积残留物。 残留物沉积物被去除。 将源极线植入在前体叠层下方的形成区域中。 该过程使得能够减少擦除存储器所需的时间。
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5.发明授权公开(公告)号：US06373311B1
公开(公告)日：2002-04-16
申请号：US09578778
申请日：2000-05-25
IPC分类号： H03K300
CPC分类号： H02M3/073 , H03K3/0315
摘要： An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals. First and second RC type circuits produce the first and second driving signals to control the transitions in the third and fourth logic signals. The oscillator circuit can be used in a switch-over control circuit for a load pump type of high-voltage generator.
摘要翻译： 振荡器电路产生第一和第二振荡逻辑信号，它们具有相同的频率并且在第一逻辑状态下不重叠。 该振荡器包括用于产生具有相反极性的第三和第四振荡逻辑信号的触发器电路，该触发器电路由第一和第二驱动逻辑信号驱动。 第一和第二逻辑门接收第三和第四逻辑信号并产生第一和第二逻辑信号，第一和第二逻辑信号中的逻辑状态转变是根据第三和第四逻辑信号的逻辑状态转换产生的。 第一和第二逻辑门被组织以便相对于第三和第四逻辑信号中的转变，在第一和第二逻辑信号中从第二逻辑状态到第一逻辑状态的转变引入延迟。 第一和第二RC型电路产生第一和第二驱动信号以控制第三和第四逻辑信号中的转变。 振荡电路可用于负载泵式高压发生器的切换控制电路。
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