Pinout architecture for a family of multiple segmented programmable
logic blocks interconnected by a high speed centralized switch matrix
    1.
    发明授权
    Pinout architecture for a family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix 失效
    用于通过高速集中式交换矩阵互连的多分段可编程逻辑块系列的引脚分配架构

    公开(公告)号:US5426335A

    公开(公告)日:1995-06-20

    申请号:US85601

    申请日:1993-06-30

    IPC分类号: H03K19/173 H03K19/177

    摘要: Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

    摘要翻译: 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元,可编程输入/输出宏单元,逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由,并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离,并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元,使得不将产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中,第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中,第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。 第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。