Pulse generator having controlled delay to control duty cycle
    1.
    发明授权
    Pulse generator having controlled delay to control duty cycle 失效
    脉冲发生器具有控制延迟以控制占空比

    公开(公告)号:US5559477A

    公开(公告)日:1996-09-24

    申请号:US528603

    申请日:1995-09-15

    摘要: Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.

    摘要翻译: 五个CMOS反相器串联连接成一个振荡器。 控制到逆变器的电流以建立反相器的门延迟,从而确定振荡器的振荡频率。 振荡器包括在锁相环中,通过选择锁相环的分频器的值来选择反相器的栅极延迟。 选择的延迟用于形成具有所需占空比的脉冲序列。

    High speed differential receiver
    2.
    发明授权
    High speed differential receiver 有权
    高速差动接收器

    公开(公告)号:US06680626B2

    公开(公告)日:2004-01-20

    申请号:US10161931

    申请日:2002-06-05

    IPC分类号: H03K522

    CPC分类号: H03K5/2481

    摘要: A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.

    摘要翻译: 具有一对交叉耦合信号调理装置的差分接收器改善了转换时间和数据信号完整性。 在一个实施例中,差分接收器包括两个信号输入节点和多个晶体管以及两个信号输出节点。 一对交叉耦合的信号调节装置耦合到晶体管并且用于减小两个输出节点之间的电压摆幅,从而将晶体管保持在饱和区域。