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    Pulse generator having controlled delay to control duty cycle
    4.
    发明授权
    Pulse generator having controlled delay to control duty cycle 失效
    脉冲发生器具有控制延迟以控制占空比

    公开(公告)号：US5559477A

    公开(公告)日：1996-09-24

    申请号：US528603

    申请日：1995-09-15

    申请人： Orhan Tozun ,  Chit-Ah Mak ,  Werner Hoeft

    发明人： Orhan Tozun ,  Chit-Ah Mak ,  Werner Hoeft

    IPC分类号： H03K3/03 ,  H03K5/156 ,  H03L7/099 ,  H03B5/02 ,  H03K3/017

    CPC分类号： H03L7/0805 ,  H03K3/0315 ,  H03K5/1565 ,  H03L7/0995

    摘要： Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.

    摘要翻译： 五个CMOS反相器串联连接成一个振荡器。 控制到逆变器的电流以建立反相器的门延迟，从而确定振荡器的振荡频率。 振荡器包括在锁相环中，通过选择锁相环的分频器的值来选择反相器的栅极延迟。 选择的延迟用于形成具有所需占空比的脉冲序列。

    Apparatus for reducing jitter of a spectrum spread clock signal and method therefor
    5.
    发明授权
    Apparatus for reducing jitter of a spectrum spread clock signal and method therefor 失效
    用于减小频谱扩展时钟信号的抖动的装置及其方法

    公开(公告)号：US5651035A

    公开(公告)日：1997-07-22

    申请号：US430575

    申请日：1995-04-28

    申请人： Orhan Tozun ,  Earl William McCune, Jr.

    发明人： Orhan Tozun ,  Earl William McCune, Jr.

    IPC分类号： H03L7/18 ,  H04L7/00 ,  H04L25/36 ,  H04L25/40

    CPC分类号： H03L7/1806

    摘要： An accumulator stores a signal representation of an accumulated angle that is incremented by an input angle in response to a reference clock pulse. The most significant bit (MSB) of the accumulated angle signals drives the input of a phase locked loop of the type that includes a loop filter, a frequency divider and a voltage controlled oscillator (VCO). A charge is injected into the loop filter during an overshoot interval during which the output of the frequency divider differs from the MSB. A compensating charge is injected into the loop filter to compensate for the charge injected during the overshoot interval. Jitter free spectrum spread clock pulses are provided by the VCO in response to the MSB.

    摘要翻译： 累加器存储响应于参考时钟脉冲而增加输入角度的累加角度的信号表示。 累积角度信号的最高有效位（MSB）驱动包括环路滤波器，分频器和压控振荡器（VCO）的类型的锁相环的输入。 在分频器的输出与MSB不同的过冲间隔期间，将电荷注入到环路滤波器中。 补偿电荷被注入到环路滤波器中以补​​偿在过冲间隔期间注入的电荷。 响应于MSB，由VCO提供无抖动频谱扩展时钟脉冲。