公开(公告)号：US6114843A

公开(公告)日：2000-09-05

申请号：US135610

申请日：1998-08-18

申请人： Robert A. Olah

发明人： Robert A. Olah

IPC分类号： G05F1/46 ,  G05F3/22

CPC分类号： G05F1/465

摘要： A voltage regulator circuit in an integrated circuit (IC) device such as a Complex Programmable Logic Device (CPLD) includes a reference voltage generator, a tuning circuit, and an output driver circuit. The reference voltage generator converts an external supply voltage provided to the IC device into a stable reference voltage. The tuning circuit converts the stable reference voltage into a desired internal supply voltage, such as the reduced voltage required by deep sub-micron transistors. The output driver circuit provides the desired internal supply voltage with sufficient current to properly power the circuits of the IC device. The tuning circuit includes an op-amp and resistive elements configured in a voltage divider configuration in the negative feedback loop of the op-amp. The output of the op-amp can be set to the desired internal supply voltage by properly sizing the resistive elements. By making at least one of the resistive elements adjustable, a variable internal supply voltage can be provided by the voltage regulator circuit.

摘要翻译： 诸如复合可编程逻辑器件（CPLD）的集成电路（IC）器件中的稳压器电路包括参考电压发生器，调谐电路和输出驱动器电路。 参考电压发生器将提供给IC器件的外部电源电压转换为稳定的参考电压。 调谐电路将稳定的参考电压转换成所需的内部电源电压，例如深亚微米晶体管所需的降低的电压。 输出驱动器电路为所需的内部电源电压提供足够的电流以正确地为IC器件的电路供电。 调谐电路包括在运算放大器的负反馈环路中以分压器配置配置的运算放大器和电阻元件。 通过适当调整电阻元件的尺寸，可以将运算放大器的输出设置为所需的内部电源电压。 通过使电阻元件中的至少一个可调，可以由电压调节器电路提供可变的内部电源电压。

公开(公告)号：US5862082A

公开(公告)日：1999-01-19

申请号：US62008

申请日：1998-04-16

申请人： Anders T. Dejenfelt ,  Diane M. Hoffstetter ,  Qi Lin ,  Robert A. Olah ,  Sholeh Diba

发明人： Anders T. Dejenfelt ,  Diane M. Hoffstetter ,  Qi Lin ,  Robert A. Olah ,  Sholeh Diba

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C13/00

CPC分类号： H01L27/115 ,  G11C16/0433

摘要： A flash electrically erasable programmable read only memory (EEPROM) cell fabricated in a semiconductor substrate. A first well region having a first conductivity type is located in the semiconductor substrate. A second well region having a second conductivity type, opposite the first conductivity type, is located in the first well region. A non-volatile memory transistor and an independently controllable access transistor are fabricated in the second well region. The non-volatile memory transistor and the access transistor are connected in series, such that the source of the access transistor is coupled to the drain of the non-volatile memory transistor. The first well region, the second well region, the non-volatile memory transistor and the access transistor are biased such that electrons are transferred from the first well region to a floating gate of the non-volatile memory transistor by Fowler-Nordheim tunneling during an erase mode, and electrons are transferred from the floating gate of the non-volatile memory transistor through the access transistor by Fowler-Nordheim tunneling during a program mode. None of the biasing voltages exceed 12 Volts, thereby enabling the flash EEPROM cell to operate in a 3.3 Volt system. In one embodiment, an array of flash EEPROM cells are fabricated in the second well region.

摘要翻译： 闪存电可擦除可编程只读存储器（EEPROM）单元，其制造在半导体衬底中。 具有第一导电类型的第一阱区位于半导体衬底中。 具有与第一导电类型相反的第二导电类型的第二阱区位于第一阱区中。 在第二阱区域中制造非易失性存储晶体管和可独立控制的存取晶体管。 非易失性存储晶体管和存取晶体管串联连接，使得存取晶体管的源极耦合到非易失性存储晶体管的漏极。 偏置第一阱区，第二阱区，非易失性存储晶体管和存取晶体管，使得电子通过Fowler-Nordheim隧道在第一阱区域转移到非易失性存储晶体管的浮置栅极 擦除模式，并且在编程模式期间，通过Fowler-Nordheim隧道，电子通过存取晶体管从非易失性存储晶体管的浮动栅极传送。 偏置电压都不超过12伏特，从而使闪存EEPROM单元能够工作在3.3伏特的系统中。 在一个实施例中，在第二阱区域中制造快闪EEPROM单元的阵列。

公开(公告)号：US06212103B1

公开(公告)日：2001-04-03

申请号：US09363075

申请日：1999-07-28

申请人： Michael G. Ahrens ,  Anders T. Dejenfelt ,  Qi Lin ,  Robert A. Olah

发明人： Michael G. Ahrens ,  Anders T. Dejenfelt ,  Qi Lin ,  Robert A. Olah

IPC分类号： G11C1604

CPC分类号： H01L27/11519 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115

摘要： A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

摘要翻译： 公开了多个闪存电可擦除可编程只读存储器（EEPROM）单元，其中金属线耦合闪存单元的源极和漏极。 这些闪存单元的读取是通过向源极施加正电压并从相关联的金属源极线读取来实现的。 提供了用于增加过度编程的闪存单元的阈值电压的软擦除方案，其防止通过向漏极施加正电压而引起的泄漏。

公开(公告)号：US06172519B2

公开(公告)日：2001-01-09

申请号：US08993596

申请日：1997-12-18

申请人： David Chiang ,  Jesse H. Jenkins, IV ,  Robert A. Olah

发明人： David Chiang ,  Jesse H. Jenkins, IV ,  Robert A. Olah

IPC分类号： H03K19173

CPC分类号： H03K19/17772 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/17764 ,  H03K19/1778

摘要： A method of operating a pin of an in-system programmable logic device (ISPLD) which includes the steps of (1) applying a predetermined voltage to the pin when the ISPLD is in a set-up mode, and (2) maintaining the last voltage applied to the pin when the ISPLD is in a normal operating mode. The ISPLD is in the set-up mode when the logic of the ISPLD has not yet been configured, or is being configured. The ISPLD is in the normal operating mode after the logic of the ISPLD has been configured. A particular ISPLD includes a pin and a logic gate having a first input terminal coupled to the pin, a second input terminal coupled to receive a control signal, and an output terminal coupled to the pin. When the ISPLD is in the set-up mode, the control signal causes the logic gate to apply a predetermined voltage to the pin. When the ISPLD is in the normal operating mode, the control signal causes the logic gate to maintain the last applied voltage on the pin.

摘要翻译： 一种操作系统可编程逻辑器件（ISPLD）的引脚的方法，其包括以下步骤：（1）当ISPLD处于建立模式时，向引脚施加预定电压，以及（2）保持最后一个 当ISPLD处于正常工作模式时，施加到引脚的电压。 当ISPLD的逻辑尚未配置或正在配置时，ISPLD处于设置模式。 在ISPLD的逻辑配置完成后，ISPLD处于正常工作模式。 特定的ISPLD包括引脚和逻辑门，其具有耦合到引脚的第一输入端，耦合以接收控制信号的第二输入端，以及耦合到引脚的输出端。 当ISPLD处于建立模式时，控制信号使逻辑门对引脚施加预定的电压。 当ISPLD处于正常工作模式时，控制信号使逻辑门保持引脚上的最后施加电压。

公开(公告)号：US06285584B1

公开(公告)日：2001-09-04

申请号：US09769613

申请日：2001-01-23

申请人： Michael G. Ahrens ,  Anders T. Dejenfelt ,  Qi Lin ,  Robert A. Olah

发明人： Michael G. Ahrens ,  Anders T. Dejenfelt ,  Qi Lin ,  Robert A. Olah

IPC分类号： G11C1604

CPC分类号： H01L27/11519 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115

摘要： A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

摘要翻译： 公开了多个闪存电可擦除可编程只读存储器（EEPROM）单元，其中金属线耦合闪存单元的源极和漏极。 这些闪存单元的读取是通过向源极施加正电压并从相关联的金属源极线读取来实现的。 提供了用于增加过度编程的闪存单元的阈值电压的软擦除方案，其防止通过向漏极施加正电压而引起的泄漏。

公开(公告)号：US06680626B2

公开(公告)日：2004-01-20

申请号：US10161931

申请日：2002-06-05

申请人： Chit-Ah Mak ,  Bingda B. Wang ,  Eric West ,  Robert A. Olah

发明人： Chit-Ah Mak ,  Bingda B. Wang ,  Eric West ,  Robert A. Olah

IPC分类号： H03K522

CPC分类号： H03K5/2481

摘要： A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.

摘要翻译： 具有一对交叉耦合信号调理装置的差分接收器改善了转换时间和数据信号完整性。 在一个实施例中，差分接收器包括两个信号输入节点和多个晶体管以及两个信号输出节点。 一对交叉耦合的信号调节装置耦合到晶体管并且用于减小两个输出节点之间的电压摆幅，从而将晶体管保持在饱和区域。

公开(公告)号：US06288526B1

公开(公告)日：2001-09-11

申请号：US09583323

申请日：2000-05-30

申请人： Robert A. Olah

发明人： Robert A. Olah

IPC分类号： G05F322

CPC分类号： G05F1/465

摘要： A voltage regulator circuit in an integrated circuit (IC) device such as a Complex Programmable Logic Device (CPLD) comprises a reference voltage generator, a tuning circuit, and an output driver circuit. The reference voltage generator converts an external supply voltage provided to the IC device into a stable reference voltage. The tuning circuit converts the stable reference voltage into a desired internal supply voltage, such as the reduced voltage required by deep sub-micron transistors. The output driver circuit provides the desired internal supply voltage with sufficient current to properly power the circuits of the IC device. The tuning circuit includes an op-amp and resistive elements configured in a voltage divider configuration in the negative feedback loop of the op-amp. The output of the op-amp can be set to the desired internal supply voltage by properly sizing the resistive elements. By making at least one of the resistive elements adjustable, a variable internal supply voltage can be provided by the voltage regulator circuit.

摘要翻译： 诸如复合可编程逻辑器件（CPLD）的集成电路（IC）器件中的稳压器电路包括参考电压发生器，调谐电路和输出驱动器电路。 参考电压发生器将提供给IC器件的外部电源电压转换为稳定的参考电压。 调谐电路将稳定的参考电压转换成所需的内部电源电压，例如深亚微米晶体管所需的降低的电压。 输出驱动器电路为所需的内部电源电压提供足够的电流以正确地为IC器件的电路供电。 调谐电路包括在运算放大器的负反馈环路中以分压器配置配置的运算放大器和电阻元件。 通过适当调整电阻元件的尺寸，可以将运算放大器的输出设置为所需的内部电源电压。 通过使电阻元件中的至少一个可调，可以由电压调节器电路提供可变的内部电源电压。