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公开(公告)号:USD373583S
公开(公告)日:1996-09-10
申请号:US38717
申请日:1995-05-10
申请人: Osamu Akiyama , Yoshito Fujii , Keiichi Koyama , Kunihiro Ohki
设计人: Osamu Akiyama , Yoshito Fujii , Keiichi Koyama , Kunihiro Ohki
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公开(公告)号:USD371552S
公开(公告)日:1996-07-09
申请号:US38715
申请日:1995-05-10
申请人: Osamu Akiyama , Yoshito Fujii , Kazuo Tsujimoto , Kazumi Osaka , Keiichi Koyama
设计人: Osamu Akiyama , Yoshito Fujii , Kazuo Tsujimoto , Kazumi Osaka , Keiichi Koyama
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公开(公告)号:USD369596S
公开(公告)日:1996-05-07
申请号:US38716
申请日:1995-05-10
申请人: Osamu Akiyama , Yoshito Fujii , Kazuo Tsujimoto , Kazumi Osaka , Keiichi Koyama
设计人: Osamu Akiyama , Yoshito Fujii , Kazuo Tsujimoto , Kazumi Osaka , Keiichi Koyama
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公开(公告)号:USD357245S
公开(公告)日:1995-04-11
申请号:US21035
申请日:1994-04-06
申请人: Seiji Usami , Yoshito Fujii , Keiichi Koyama
设计人: Seiji Usami , Yoshito Fujii , Keiichi Koyama
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公开(公告)号:USD351156S
公开(公告)日:1994-10-04
申请号:US12211
申请日:1993-07-08
申请人: Seiji Usami , Yoshito Fujii , Keiichi Koyama
设计人: Seiji Usami , Yoshito Fujii , Keiichi Koyama
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公开(公告)号:USD372026S
公开(公告)日:1996-07-23
申请号:US38718
申请日:1995-05-10
申请人: Osamu Akiyama , Yoshito Fujii , Kazumi Osaka , Yutaka Ito
设计人: Osamu Akiyama , Yoshito Fujii , Kazumi Osaka , Yutaka Ito
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公开(公告)号:USD680087S1
公开(公告)日:2013-04-16
申请号:US29410027
申请日:2012-01-03
申请人: Yoshito Fujii , Katsuhiro Iida , Tohru Ohtani , Hiroshi Gomi
设计人: Yoshito Fujii , Katsuhiro Iida , Tohru Ohtani , Hiroshi Gomi
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8.Semiconductor device having a multilevel interconnect structure and method for fabricating the same 失效
标题翻译: 具有多层互连结构的半导体器件及其制造方法公开(公告)号:US08304908B2
公开(公告)日:2012-11-06
申请号:US12382624
申请日:2009-03-19
申请人: Junichi Koike , Yoshito Fujii , Jun Iijima , Noriyoshi Shimizu , Kazuyoshi Maekawa , Koji Arita , Ryotaro Yagi , Masaki Yoshimaru
发明人: Junichi Koike , Yoshito Fujii , Jun Iijima , Noriyoshi Shimizu , Kazuyoshi Maekawa , Koji Arita , Ryotaro Yagi , Masaki Yoshimaru
CPC分类号: H01L21/76853 , H01L21/288 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76861 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
摘要翻译: 半导体器件中的多层互连结构包括形成在半导体晶片上的第一绝缘层,形成在第一绝缘层上的Cu互连层,形成在Cu互连层上的第二绝缘层和形成在界面处的金属氧化物层 在Cu互连层和第二绝缘层之间。 金属氧化物层通过在Cu互连层上浸渍诸如Sn或Zn的金属,然后在氧化气氛中对镀层进行热处理而形成。
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公开(公告)号:USD552050S1
公开(公告)日:2007-10-02
申请号:US29261811
申请日:2006-06-21
申请人: Yoshito Fujii , Tohru Ohtani , Hiroshi Gomi
设计人: Yoshito Fujii , Tohru Ohtani , Hiroshi Gomi
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公开(公告)号:USD351157S
公开(公告)日:1994-10-04
申请号:US16404
申请日:1993-12-16
申请人: Seiji Usami , Yoshito Fujii , Yasushi Fukuda
设计人: Seiji Usami , Yoshito Fujii , Yasushi Fukuda
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