公开(公告)号：US20240282626A1

公开(公告)日：2024-08-22

申请号：US18648979

申请日：2024-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Hsien Huang ,  I-Li Chen ,  Pin-Wen Chen ,  Yuan-Chen Hsu ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76861 ,  H01L21/76805 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L23/53266

摘要： A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening

公开(公告)号：US11901227B2

公开(公告)日：2024-02-13

申请号：US17497702

申请日：2021-10-08

申请人： Lam Research Corporation

发明人： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC分类号： H01L29/768 ,  H01L21/768 ,  H01L21/285 ,  H01L21/321 ,  H01L21/324 ,  C23C16/04 ,  C23C16/50 ,  H10B41/27 ,  H10B41/35 ,  C23C16/00

CPC分类号： H01L21/76879 ,  C23C16/00 ,  C23C16/045 ,  C23C16/50 ,  H01L21/28556 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76876 ,  H01L21/76898 ,  H10B41/27 ,  H10B41/35 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

公开(公告)号：US11869808B2

公开(公告)日：2024-01-09

申请号：US17481362

申请日：2021-09-22

申请人： International Business Machines Corporation

发明人： Lawrence A. Clevenger ,  Brent Anderson ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76897 ,  H01L21/7681 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76879 ,  H01L23/5226 ,  H01L21/76816

摘要： An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.

公开(公告)号：US20230335434A1

公开(公告)日：2023-10-19

申请号：US18208409

申请日：2023-06-12

申请人： Applied Materials, Inc.

发明人： Anqing Cui ,  Dien-Yeh Wu ,  Wei V. Tang ,  Yixiong Yang ,  Bo Wang

IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L21/02 ,  C23C16/02 ,  C23C16/455 ,  C23C16/458 ,  H01L21/285 ,  H01L21/687 ,  H01L23/532

CPC分类号： H01L21/76826 ,  H01L21/4871 ,  H01L21/0228 ,  C23C16/02 ,  C23C16/45553 ,  C23C16/4584 ,  H01L21/28568 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76877 ,  H01L23/53266

摘要： Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate.

公开(公告)号：US20230260837A1

公开(公告)日：2023-08-17

申请号：US17998255

申请日：2021-05-03

申请人： Lam Research Corporation

发明人： Hyungjun Hur ,  Pooja Tilak ,  Shantinath Ghongadi ,  Cian Sweeney

IPC分类号： H01L21/768 ,  C25D7/12 ,  C25D17/00 ,  C25D21/12

CPC分类号： H01L21/76873 ,  C25D7/123 ,  C25D17/001 ,  C25D21/12 ,  H01L21/76861 ,  H01L21/76877

摘要： Various embodiments include methods and apparatuses to moisturize a substrate prior to an electrochemical deposition process. In one embodiment, a method to control substrate wettability includes placing a substrate in a humidification environment, controlling the humidification environment to moisturize a surface of the substrate; and placing the substrate into a plating cell. Other methods and systems are disclosed.

公开(公告)号：US20180171501A1

公开(公告)日：2018-06-21

申请号：US15832504

申请日：2017-12-05

申请人： Ebara Corporation

发明人： Yasuyuki Masuda ,  Masashi Shimoyama ,  Takashi Kishi

IPC分类号： C25D5/02 ,  C25D17/06 ,  C25D17/12 ,  C25D21/04 ,  C25D21/10 ,  C25D21/14 ,  H01L21/288

CPC分类号： C25D5/02 ,  C25D17/001 ,  C25D17/06 ,  C25D17/12 ,  C25D21/04 ,  C25D21/10 ,  C25D21/14 ,  H01L21/288 ,  H01L21/76861 ,  H01L21/76873

摘要： There is provided a plating apparatus for performing plating treatment on a substrate having a resist pattern. The plating apparatus includes: a pretreatment unit for causing a surface of the substrate to be brought into contact with a pretreatment solution; and a plating bath in which the plating treatment is performed on the substrate having a surface to be treated which is brought into contact with the pretreatment solution. The pretreatment unit includes: a holding table for holding the substrate with the surface to be treated facing upward; a motor for rotating the holding table; a hydrophilizing treatment portion for irradiating ultraviolet rays to the surface to be treated; and a pretreatment solution supply portion for supplying the pretreatment solution to the surface to be treated which is hydrophilized by the hydrophilizing treatment portion.

公开(公告)号：US09978685B2

公开(公告)日：2018-05-22

申请号：US15381752

申请日：2016-12-16

申请人： Applied Materials, Inc.

发明人： Yihong Chen ,  Kelvin Chan ,  Srinivas Gandikota

IPC分类号： H01L21/28 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  H01L31/18

CPC分类号： H01L23/53266 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76876 ,  H01L31/18

摘要： Methods for depositing a metal film comprising forming an amorphous silicon layer as a nucleation layer and/or glue layer on a substrate. Some embodiments further comprise the incorporation of a glue layer to increase the ability of the amorphous silicon layer and metal layer to stick to the substrate.

公开(公告)号：US20180130707A1

公开(公告)日：2018-05-10

申请号：US15573108

申请日：2015-06-18

申请人： Intel Corporation

发明人： Scott B. CLENDENNING ,  Martin M. MITAN ,  Timothy E. GLASSMAN ,  Flavio GRIGGIO ,  Grant M. KLOSTER ,  Kent N. FRASURE ,  Florian GSTREIN ,  Rami HOURANI

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L21/311

CPC分类号： H01L21/76879 ,  C23C16/045 ,  H01L21/28 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76876 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2221/1063

摘要： Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.

公开(公告)号：US20180097068A1

公开(公告)日：2018-04-05

申请号：US15683237

申请日：2017-08-22

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： MING ZHOU

IPC分类号： H01L29/16 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H01L21/768

CPC分类号： H01L29/1606 ,  H01L21/02488 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/469 ,  H01L21/76861 ,  H01L21/76876 ,  H01L21/823431 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78684 ,  H01L45/06

摘要： The present disclosure relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor. The method includes forming a growth substrate by providing a substrate structure containing a sacrificial substrate, a first dielectric layer on the sacrificial substrate, and a plurality of recesses formed through the first dielectric layer and into the sacrificial substrate, by forming a buffer layer covering exposes surfaces of the plurality of recesses, by selectively growing a graphene layer on the buffer layer, and by filling the plurality of recesses with a second dielectric layer. The method further includes attaching the growth substrate to a bonding substrate such that the second dielectric layer attaches to the bonding substrate; removing the sacrificial substrate; and removing the buffer layer so as to expose the graphene layer. The method of present disclosure avoids adverse effects from patterning graphene by using selective growth of graphene on a patterned buffer layer.

公开(公告)号：US09899258B1

公开(公告)日：2018-02-20

申请号：US15282440

申请日：2016-09-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Wen Wu ,  Sung-Li Wang ,  Min-Hsiu Hung ,  Yida Li ,  Chih-Wei Chang ,  Huang-Yi Huang ,  Cheng-Tung Lin ,  Jyh-Cherng Sheu ,  Yee-Chia Yeo ,  Chi On Chui

IPC分类号： H01L21/768 ,  H01L21/3213

CPC分类号： H01L21/76879 ,  H01L21/32131 ,  H01L21/76847 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481

摘要： Overhang reduction methods are disclosed. In some embodiments, a method includes forming a recess in a dielectric layer, the recess defining first sidewalls of the dielectric layer. The method also includes depositing a first conductive layer over an upper surface of the dielectric layer and the sidewalls of the dielectric layer, the first conductive layer having a first overhang, removing the first overhang of the first conductive layer using an etchant selected from the group consisting of a halide of the first conductive layer, Cl2, BCl3, SPM, SC1, SC2, and combinations thereof, and filling the recess with a second conductive layer.