公开(公告)号：US20200149797A1

公开(公告)日：2020-05-14

申请号：US16740232

申请日：2020-01-10

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Seiji YAMAHIRA ,  Yuta MORIURA ,  Akihiro ODAGAWA ,  Kazuya NIKI ,  Shinobu MASUDA ,  Yui SAWADA ,  Keiji NOINE

IPC: F25D11/00 ,  G06N20/00 ,  G06K9/00

Abstract: A food management system that manages food items in a refrigerator includes: a pressure-sensitive sensor that acquires information including shapes, weights, and positions of the food items; a comparator that performs comparison of the information acquired at different times; and an identifier that identifies at least one of (i) fluctuations in the number of food items or (ii) presence or absence of the food items.

公开(公告)号：US20210176413A1

公开(公告)日：2021-06-10

申请号：US17183213

申请日：2021-02-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akito INOUE ,  Yutaka HIROSE ,  Seiji YAMAHIRA

IPC: H04N5/355 ,  H04N5/378 ,  H04N5/369

Abstract: The photosensor includes an APD that has a multiplication region including a photoelectric converter and includes a first capacitor connected to the multiplication region in parallel, and a first transistor connected between the APD and a first power supply (voltage VC). The first transistor applies a reverse bias of a power supply voltage (VC-VA), which is larger than a breakdown voltage VBD, between an anode and a cathode of the APD during a bias setting period by connecting the APD to the first power supply, and stops an avalanche multiplication phenomenon during a light exposing period by disconnecting the APD from the first power supply to accumulate charges generated by the avalanche multiplication phenomenon in the first capacitor.

公开(公告)号：US20170187939A1

公开(公告)日：2017-06-29

申请号：US15461159

申请日：2017-03-16

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Shigetaka KASUGA ,  Seiji YAMAHIRA ,  Yoshihisa KATO

IPC: H04N5/235 ,  G01J1/44

Abstract: A solid-state imaging device includes a detector, a count value storage, and a reader. The detector includes an avalanche amplification type light receiving element that detects a photon, and a resetter that resets an output potential of the light receiving element, and outputs a digital signal that indicates the presence or absence of incidence of a photon on the light receiving element. The count value storage performs counting by converting the digital signal output from the detector to an analog voltage, and stores the result of counting as a count value. The reader outputs an analog signal indicating the count value.

公开(公告)号：US20220014704A1

公开(公告)日：2022-01-13

申请号：US17484549

申请日：2021-09-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Seiji YAMAHIRA

IPC: H04N5/3745 ,  H01L27/146 ,  H01L31/10

Abstract: An imaging processing circuit includes a restrictor (an offset circuit). The restrictor is configured to restrict at least one of a maximum value or a minimum value for an output signal from a photoelectric converter which is configured to convert a photon into an electric charge and whose conversion ratio from the photon to the electric charge is variable. The restrictor restricts a difference between the maximum value and the minimum value of the output signal from the photoelectric converter when the conversion ratio is a first conversion ratio to be smaller than a difference between the maximum value and the minimum value of the output signal from the photoelectric converter when the conversion ratio is a second conversion ratio. The second conversion ratio is less than the first conversion ratio.

公开(公告)号：US20180278877A1

公开(公告)日：2018-09-27

申请号：US15995614

申请日：2018-06-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Seiji YAMAHIRA

IPC: H04N5/378 ,  H04N5/374 ,  H04N5/355 ,  H01L27/146

CPC classification number: H04N5/378 ,  H01L27/14609 ,  H04N5/355 ,  H04N5/374 ,  H04N5/3742

Abstract: A solid-state image-capturing device includes a pixel array including a plurality of pixel circuits arranged in rows and columns. Each pixel circuit includes: a photoelectric conversion element that generates an electric charge through photoelectric conversion between a bias terminal and a first node, and amplifies the electric charge according to a bias voltage applied via the bias terminal and the first node; a transfer circuit that electrically connects the first node to a second node according to a first control signal; a reset circuit that applies a reset voltage to the second node according to a second control signal; an output circuit that reads out a voltage of the second node according to a third control signal; and an analog memory that is electrically connected to the second node according to a fourth control signal.