公开(公告)号：US11782852B2

公开(公告)日：2023-10-10

申请号：US17208354

申请日：2021-03-22

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tadashi Ono ,  Isao Kato ,  Yoshihisa Inagaki ,  Shuichi Ohki

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/4282 ,  G06F2213/0026

Abstract: When a part of a signal line of a first interface and a part of a signal line of a second interface share a signal line and there is a memory connected to both the interfaces, initialization of the second interface and initialization of the memory are executed in parallel following initialization of the first interface.