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公开(公告)号：US11115611B2
公开(公告)日：2021-09-07
申请号：US15930152
申请日：2020-05-12
发明人： Yosuke Higashi , Norihiko Sumitani
IPC分类号： H04N5/374 , H04N5/3745 , H03M1/56 , H04N5/378
摘要： A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.
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公开(公告)号：US11265502B2
公开(公告)日：2022-03-01
申请号：US15930251
申请日：2020-05-12
发明人： Norihiko Sumitani , Yosuke Higashi
IPC分类号： H04N5/3745 , H04N5/376 , H04N5/378
摘要： A solid-state imaging device includes: a latch circuit that holds a digital signal of pixel data, the digital signal having 1 bit; a driver circuit that outputs the digital signal held in the latch circuit to a read bit line pair; a sense amplifier connected to the read bit line pair; and a selector circuit that selects whether the digital signal output from the sense amplifier is to be output in normal form or in inverted form.
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公开(公告)号：US20200275045A1
公开(公告)日：2020-08-27
申请号：US15930152
申请日：2020-05-12
发明人： Yosuke Higashi , Norihiko Sumitani
IPC分类号： H04N5/3745 , H04N5/378 , H03M1/56
摘要： A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.
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