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    Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices
    1.
    发明申请
    Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices 有权
    用于多VT设备的双聚合图案化的标准单元架构

    公开(公告)号：US20120180016A1

    公开(公告)日：2012-07-12

    申请号：US13004460

    申请日：2011-01-11

    申请人： PR Chidambaram ,  Prayag B. Patel ,  Foua Vang ,  Pratyush Kamal ,  Chock H Gan ,  Chethan Swamynathan

    发明人： PR Chidambaram ,  Prayag B. Patel ,  Foua Vang ,  Pratyush Kamal ,  Chock H Gan ,  Chethan Swamynathan

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.

    摘要翻译： 使用包括具有不同电压阈值的装置的标准单元架构制造的装置可以包括与第一通道长度相关联的第一组折线，其中第一组折线中的每个折线被基本恒定的间距分开。 该装置还可以包括与第二通道长度相关联并与第一组折线对准的第二组折线，其中第二组折线中的每条折线被基本恒定的间距横向隔开。 该装置还可以包括在第一组折线下方的第一有源区域和第二组折线下方的第二有源区域，其中第一有源区域和第二有源区域被分开小于170nm的距离。

    Standard cell architecture using double poly patterning for multi VT devices
    2.
    发明授权
    Standard cell architecture using double poly patterning for multi VT devices 有权
    标准单元架构，采用双重多晶格形成多VT器件

    公开(公告)号：US08610176B2

    公开(公告)日：2013-12-17

    申请号：US13004460

    申请日：2011-01-11

    申请人： Prayag B. Patel ,  Pratyush Kamal ,  Foua Vang ,  Chock H. Gan ,  Pr Chidambaram ,  Chethan Swamynathan

    发明人： Prayag B. Patel ,  Pratyush Kamal ,  Foua Vang ,  Chock H. Gan ,  Pr Chidambaram ,  Chethan Swamynathan

    IPC分类号： H01L27/00 ,  H01L21/768

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.

    摘要翻译： 使用包括具有不同电压阈值的装置的标准单元架构制造的装置可以包括与第一通道长度相关联的第一组折线，其中第一组折线中的每个折线被基本恒定的间距分开。 该装置还可以包括与第二通道长度相关联并与第一组折线对准的第二组折线，其中第二组折线中的每条折线被基本恒定的间距横向隔开。 该装置还可以包括在第一组折线下方的第一有源区域和第二组折线下方的第二有源区域，其中第一有源区域和第二有源区域之间的距离小于170nm。

    Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics
    5.
    发明授权
    Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics 失效
    用于表征和减少对电池电特性的接近效应的方法和装置

    公开(公告)号：US08584075B2

    公开(公告)日：2013-11-12

    申请号：US13027359

    申请日：2011-02-15

    申请人： Animesh Datta ,  Pratyush Kamal ,  Prayag B. Patel ,  Xiaonan Zhang

    发明人： Animesh Datta ,  Pratyush Kamal ,  Prayag B. Patel ,  Xiaonan Zhang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5036

    摘要： Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.

    摘要翻译： 电路元件的特征在于接近上下文对电特性的影响。 基于表征，获得邻近上下文单元模型和相应的建模电特性值。 逻辑单元根据邻近情景单元模型进行表征和建模。 可选地，电特性可以是其他参数之间的时间延迟，泄漏，动态功率或耦合噪声。