公开(公告)号：US06606044B2

公开(公告)日：2003-08-12

申请号：US10034909

申请日：2002-01-02

申请人： William J. Roeckner ,  Pallab Midya ,  Poojan A. Wagh ,  William J. Rinderknecht

发明人： William J. Roeckner ,  Pallab Midya ,  Poojan A. Wagh ,  William J. Rinderknecht

IPC分类号： H03M300

CPC分类号： H03F3/2175 ,  H03F2200/331 ,  H03M1/822 ,  H03M5/08

摘要： A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.

摘要翻译： 提供了一种用于脉宽调制（PWM）信号（30,130）的方法和装置。 输入是作为调制信号（24,124）的数字信号。 在所示的形式中，调制输入信号是PDM信号或PCM信号。 在本发明的一个实施例中，PCM至PWM转换器（16,116）包括占空比电路（48）的校正。 所使用的方法可以包括在预测，插值和校正之后获得的值的递归。 数模转换系统（10）使用PDM到PWM转换器（20），其在全数字域中工作，并且不包括模拟电路。

公开(公告)号：US06504427B2

公开(公告)日：2003-01-07

申请号：US09872283

申请日：2001-05-31

申请人： Pallab Midya ,  William J. Roeckner ,  Poojan A. Wagh

发明人： Pallab Midya ,  William J. Roeckner ,  Poojan A. Wagh

IPC分类号： H03F338

CPC分类号： H03F3/2175

摘要： A switching amplifier (15) includes a power stage (18) and a digital correction circuit (16). The digital correction circuit (16) is for correcting nonlinearity and power supply noise introduced into a digital signal during power stage amplification. The digital correction circuit (16) receives a digital pulse modulated input signal from a processor (14) and an amplified pulse modulated output signal from the power stage (18), and performs a discrete-time pulse edge correction on the digital pulse modulated input signal to provide a corrected digital pulse modulated signal. The corrected digital pulse modulated signal is used as an input for the power stage (18).

公开(公告)号：US06614323B2

公开(公告)日：2003-09-02

申请号：US09995305

申请日：2001-11-27

申请人： Poojan A. Wagh ,  Pallab Midya ,  Patrick Rakers

发明人： Poojan A. Wagh ,  Pallab Midya ,  Patrick Rakers

IPC分类号： H03K700

CPC分类号： H03C3/40

摘要： A device for implementing a method for receiving a complex baseband signal in analog form or in digital form, and providing a pulse modulated signal as a linear modulation of the complex baseband signal is disclosed. First, a complex modulated signal as a function of the complex baseband signal is generated. Second, a bandlimited exponential signal as a function of the complex modulated signal as computed with a truncated Taylor series for an exponential is generated, or a coefficient vector as a function of the complex modulated signal is generated. Finally, a pulse modulated signal as either a function of the bandlimited exponential signal or the coefficient vector is generated.

摘要翻译： 公开了一种用于实现用于以模拟形式或数字形式接收复基带信号的方法，并提供脉冲调制信号作为复基带信号的线性调制的装置。 首先，生成作为复基带信号的函数的复调制信号。 第二，产生作为用指数的截断泰勒级数计算的复调制信号的函数的带限指数信号，或者产生作为复调制信号的函数的系数向量。 最后，产生作为带限指数信号或系数矢量的函数的脉冲调制信号。

公开(公告)号：US06587010B2

公开(公告)日：2003-07-01

申请号：US09995123

申请日：2001-11-27

申请人： Poojan A. Wagh ,  Pallab Midya ,  Patrick Rakers

发明人： Poojan A. Wagh ,  Pallab Midya ,  Patrick Rakers

IPC分类号： H03B104

CPC分类号： H03K7/00 ,  H04B1/04

摘要： A modulated signal source for implementing A modulated signal method of a generating a modulated signal having a radio frequency based upon a linear mixing of signals is disclosed. An in-phase pulse signal modulator of the modulated signal source provides an in-phase pulse modulated signal in response to a reception of a baseband in-phase signal and an in-phase clock signal with the in-phase clock signal and the in-phase pulse modulated signal being synchronized. A quadrature pulse signal modulator of the modulated signal source provides a quadrature pulse modulated signal in response to a reception of a baseband quadrature signal and a quadrature clock signal with the quadrature clock signal and the quadrature pulse modulated signal being synchronized. A switch signal generator of the modulated signal source generates an in-phase switch signal and a quadrature switch signal in response to a reception of the in-phase clock signal, the in-phase pulse modulated signal, the quadrature clock signal, and the quadrature pulse modulated signal. The in-phase clock signal and the in-phase switch signal are synchronized, and the quadrature clock signal and the quadrature switch signal are synchronized. A radio frequency signal generator of the modulated signal source provides one or more modulated signals having a radio frequency in response to either a reception the in-phase switch signal and the quadrature phase signal, or a reception of a switch signal as a function of the in-phase switch signal and the quadrature phase signal.

公开(公告)号：US06549085B1

公开(公告)日：2003-04-15

申请号：US09995122

申请日：2001-11-27

申请人： Poojan A. Wagh ,  Pallab Midya ,  Patrick Rakers

发明人： Poojan A. Wagh ,  Pallab Midya ,  Patrick Rakers

IPC分类号： H03K708

CPC分类号： H03K7/10

摘要： A device for implementing a method for generating a pulse width modulated signal based upon a natural sampling technique is disclosed. First, a complex baseband signal is received by the device. Second, the device computes a first pulse edge vector and a second pulse edge vector as a function of the baseband signal. Third, the device computes a first set of natural sampling points as a function of the first pulse edge vector and computes a second set of natural sampling points as a function of the second pulse edge vector. These computations can involve one or more detections of a jump k&pgr; within the first pulse edge vector and/or the second pulse edge vector. Finally, the pulse width modulated signal is generated with pulse edges corresponding to the first set of natural sampling points and the second set of natural sampling points.

摘要翻译： 公开了一种用于实现基于自然采样技术产生脉宽调制信号的方法的装置。 首先，设备接收到复杂的基带信号。 第二，该装置计算作为基带信号的函数的第一脉冲边缘向量和第二脉冲边缘向量。 第三，设备根据第一脉冲边缘向量计算第一组自然采样点，并计算作为第二脉冲边缘向量的函数的第二组自然采样点。 这些计算可涉及在第一脉冲边缘向量和/或第二脉冲边缘向量内的跳转kpi的一个或多个检测。 最后，利用对应于第一组自然采样点和第二组自然采样点的脉冲边缘产生脉宽调制信号。

公开(公告)号：US07352311B2

公开(公告)日：2008-04-01

申请号：US11507919

申请日：2006-08-22

申请人： Matthew R. Miller ,  Pallab Midya ,  Poojan A. Wagh

发明人： Matthew R. Miller ,  Pallab Midya ,  Poojan A. Wagh

IPC分类号： H03M3/00

CPC分类号： H03M3/432

摘要： A system for a continuous time noise shaping analog-to-digital converter (“ADC”) with a suppressed carrier pulse width modulated (“PWM”) quantizer is disclosed. In particular, a suppressed carrier feedback signal may expand the dynamic range of a sigma delta modulated ADC and enhance the stability of the noise shaping loop.

摘要翻译： 公开了一种具有抑制载波脉宽调制（“PWM”）量化器的连续时间噪声整形模数转换器（“ADC”）的系统。 特别地，抑制的载波反馈信号可以扩展Σ-Δ调制ADC的动态范围，并增强噪声整形环路的稳定性。

公开(公告)号：US20080048898A1

公开(公告)日：2008-02-28

申请号：US11507919

申请日：2006-08-22

申请人： Matthew R. Miller ,  Pallab Midya ,  Poojan A. Wagh

发明人： Matthew R. Miller ,  Pallab Midya ,  Poojan A. Wagh

IPC分类号： H03M3/00

CPC分类号： H03M3/432

摘要： A system for a continuous time noise shaping analog-to-digital converter (“ADC”) with a suppressed carrier pulse width modulated (“PWM”) quantizer is disclosed. In particular, a suppressed carrier feedback signal may expand the dynamic range of a sigma delta modulated ADC and enhance the stability of the noise shaping loop.

摘要翻译： 公开了一种具有抑制载波脉宽调制（“PWM”）量化器的连续时间噪声整形模数转换器（“ADC”）的系统。 特别地，抑制的载波反馈信号可以扩展Σ-Δ调制ADC的动态范围，并增强噪声整形环路的稳定性。

公开(公告)号：US20090102549A1

公开(公告)日：2009-04-23

申请号：US11875998

申请日：2007-10-22

申请人： Pallab Midya ,  Theresa Paulo ,  William J. Roeckner

发明人： Pallab Midya ,  Theresa Paulo ,  William J. Roeckner

IPC分类号： H03F3/38

CPC分类号： H03F3/217

摘要： A switching amplifier includes a power stage, a low pass filter, a combining circuit, and a feedback correction circuit. The power stage has an input terminal and an output terminal. The low pass filter has an input terminal coupled to the output terminal of the power stage, and an output terminal for providing a filtered pulse width modulated signal. The combining circuit has a first input terminal coupled to the output terminal of the power stage, a second input terminal coupled to the output terminal of the low pass filter, and an output terminal. The feedback correction circuit has a first input terminal for receiving a reference pulse width modulated signal, a second input terminal coupled to the output terminal of the combining circuit, and an output terminal coupled to the input terminal of the power stage.

摘要翻译： 开关放大器包括功率级，低通滤波器，组合电路和反馈校正电路。 功率级具有输入端子和输出端子。 低通滤波器具有耦合到功率级的输出端的输入端和用于提供经滤波的脉宽调制信号的输出端。 组合电路具有耦合到功率级的输出端的第一输入端，耦合到低通滤波器的输出端的第二输入端和输出端。 反馈校正电路具有用于接收参考脉冲宽度调制信号的第一输入端子，耦合到组合电路的输出端子的第二输入端子和耦合到功率级输入端子的输出端子。

公开(公告)号：US07312654B2

公开(公告)日：2007-12-25

申请号：US11314203

申请日：2005-12-20

申请人： William J. Roeckner ,  Pallab Midya ,  Patrick L. Rakers ,  Lawrence E. Connell ,  Daniel A. Mavencamp ,  Bradley C. Stewart

发明人： William J. Roeckner ,  Pallab Midya ,  Patrick L. Rakers ,  Lawrence E. Connell ,  Daniel A. Mavencamp ,  Bradley C. Stewart

IPC分类号： H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/305 ,  H03F3/2171 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/351 ,  H03K17/161

摘要： A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down, essentially the reverse sequence is provided.

摘要翻译： 提供一种闭环音频放大器系统以及在不产生可听见的伪影的情况下对系统加电/下电的方法。 在上电期间，向连接到扬声器的每个输出端提供预偏置电压以将电压增加到额定输出电平。 然后以50％占空比驱动高阻抗开关。 输出端的反馈信号被提供给一个伺服控制器，可以对输出电压进行微调。 然后，在四分之一周期的时间，以50％的占空比驱动低阻抗开关。 反馈环路的顺序取决于驱动高阻抗或低阻抗开关中的哪一个。 然后在将要放大的音频信号提供给系统之前，去除预偏置电压。 开关的驱动时序是可编程的。 为了断电，基本上提供了相反的顺序。

公开(公告)号：US20110012674A1

公开(公告)日：2011-01-20

申请号：US12503816

申请日：2009-07-15

申请人： Pallab Midya ,  William J. Roeckner

发明人： Pallab Midya ,  William J. Roeckner

IPC分类号： H03F3/38

CPC分类号： H03G3/348 ,  H03F1/305 ,  H03F3/217

摘要： A switching audio amplifier circuit drives a switching audio amplifier stage using a digital PWM signal from an audio source. A PWM duty ratio modifier modifies an edge timing of the digital PWM signal to produce a modified digital PWM signal. A mode switch switches between the digital PWM signal and the modified digital PWM signal in a way that masks audible noise such as clicks and pops at power-up and power-down of the switching audio amplifier. An integrating error amplifier compares a difference between the digital PWM signal and an amplified PWM signal and integrates the difference to control the edge timing modified by the PWM duty ratio modifier. A mode controller can apply an offset signal to the integrating error amplifier and can control the switching of the mode switch.

摘要翻译： 开关音频放大器电路使用来自音频源的数字PWM信号驱动开关音频放大器级。 PWM占空比修改器修改数字PWM信号的边沿定时，以产生修改的数字PWM信号。 模式开关在数字PWM信号和修改的数字PWM信号之间切换，以掩盖在开关音频放大器的上电和掉电时的可听到的噪声，例如咔嗒声和咔嗒声。 积分误差放大器将数字PWM信号和放大的PWM信号之间的差异进行比较，并将差值积分，以控制由PWM占空比修正器修改的边沿时序。 模式控制器可以将偏移信号应用于积分误差放大器，并可以控制模式开关的切换。