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    Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof
    1.
    发明授权
    Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof 失效
    分割主机指令集以实现其基于微处理器的仿真的方法

    公开(公告)号：US4514803A

    公开(公告)日：1985-04-30

    申请号：US371634

    申请日：1982-04-26

    申请人： Palmer W. Agnew ,  Joseph P. Buonomo ,  Steven R. Houghtalen ,  Anne S. Kellerman ,  Raymond E. Losinger ,  James W. Valashinas

    发明人： Palmer W. Agnew ,  Joseph P. Buonomo ,  Steven R. Houghtalen ,  Anne S. Kellerman ,  Raymond E. Losinger ,  James W. Valashinas

    IPC分类号： G06F9/455 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

    CPC分类号： G06F9/223 ,  G06F9/26 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3877 ,  G06F9/3879

    摘要： Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. A mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is economically feasible to have several copies of a complex data flow and control store mechanism.

    摘要翻译： 描述了将LSI和微处理器应用于基于微处理器的LSI实现主机处理器的方法。 大型机指令集被划分为两个或更多个子集，每个子​​集可以由具有特殊片上微码的微处理器或由运行用于该目的而编写的程序的标准现成的微处理器来实现。 或者，一个或多个子集可以由单个微处理器来实现。 此外，分割指令集的子集可以通过模拟软件，片外垂直或水平微代码，或者由原语来实现。 但是，然而，实现分区，其最终结果是将与最常用的指令子集相关联的关键流程路径尽可能短地限制到单个芯片。 这种方法的应用需要分区，这使得每个识别的高性能子集在当前技术状态下在一个微处理器上可执行，这种方式能够在所有微处理器之间快速传递控制，这种方法能够在所有微处理器之间来回传递数据 所有的微处理器，以及在经济上具有复制数据流和控制存储机制的几个拷贝的技术。

    Storage selection override apparatus for a multimicroprocessor implemented data processing system
    3.
    发明授权
    Storage selection override apparatus for a multimicroprocessor implemented data processing system 失效
    用于多重处理器实现的数据处理系统的存储选择覆盖装置

    公开(公告)号：US4591982A

    公开(公告)日：1986-05-27

    申请号：US527053

    申请日：1983-08-29

    申请人： Joseph P. Buonomo ,  Steven R. Houghtalen ,  Raymond E. Losinger ,  James W. Valashinas

    发明人： Joseph P. Buonomo ,  Steven R. Houghtalen ,  Raymond E. Losinger ,  James W. Valashinas

    IPC分类号： G06F9/455 ,  G06F9/26 ,  G06F9/318 ,  G06F9/38 ,  G06F15/16 ,  G06F9/00 ,  G06F12/02

    CPC分类号： G06F9/3017 ,  G06F9/26 ,  G06F9/3802 ,  G06F9/3877 ,  G06F9/3879

    摘要： The performance of a multimicroprocessor implemented data processing system that emulates a mainframe is enhanced by providing a pair of override latches that serve to steer accesses between main and control storage for instruction fetch and operand acquisition in a manner that minimizes the complexity and size of microprocessor interface microcoding. This is achieved by connecting the instruction and operand override latches between a primary microprocessor, a secondary microprocessor, off-chip control storage belonging to the secondary microprocessor, particularly memory mapped private storage therein, and main storage. The override latches are made responsive, via microcode provided for that purpose, to the type and cause of each memory access. The override latches are set or reset by a memory mapped write to a predefined address in the secondary control store after being enabled by control lines responsive to the particular microprocessor action being taken. When set, the instruction override latch directs all expected primary processor main storage instruction fetches to control store. When set, the operand override latch directs all expected primary processor main storage operand accesses to control store. As appropriate for instruction execution, either one or both of the primary or secondary microprocessors can thereby be transparently latched to main or control storage.

    摘要翻译： 通过提供一对超控锁存器来增强仿真主机的多处理器实现的数据处理系统的性能，该对超控锁存器用于控制主存储器和控制存储器之间的访问，以便以最小化微处理器接口的复杂度和大小的方式进行指令提取和操作数采集 微码。 这是通过在主微处理器，二级微处理器，属于次级微处理器的片外控制存储器，特别是其中的存储器映射私有存储器和主存储器之间连接指令和操作数超驰锁存器来实现的。 通过为此目的提供的微码，覆盖锁存器响应于每个存储器访问的类型和原因。 在通过响应于采取特定微处理器动作的控制线使能之后，通过存储器映射写入次控制存储器中的预定义地址来设置或复位超驰锁存器。 设置时，指令重写锁存器将所有预期的主处理器主存储指令提取指向控制存储。 当设置时，操作数覆盖锁存器将所有预期的主处理器主存储操作数访问指向控制存储。 适合于指令执行，主处理器或辅助微处理器中的一个或两个可以被透明地锁存到主存储器或控制存储器。