公开(公告)号：US09401778B2

公开(公告)日：2016-07-26

申请号：US14534921

申请日：2014-11-06

Applicant: Panasonic Corporation

Inventor： Yoshito Hirai ,  Kouji Okamoto

IPC: H04B1/00 ,  H04L1/00 ,  H03F3/217 ,  H03F3/00 ,  H04L27/36 ,  H03F1/32

CPC classification number: H04L1/0042 ,  H03F1/3247 ,  H03F3/005 ,  H03F3/217 ,  H04L1/0043 ,  H04L27/364

Abstract: A storage unit stores a first lookup table including a plurality of correction coefficients for I codes, and stores a second lookup table including a plurality of correction coefficients for Q codes. Each of the correction coefficients for I codes and each of the correction coefficients for Q codes are complex numbers. A distortion compensation unit compensates, with one of the plurality of correction coefficients for I codes, distortion of an I code of a transmission signal to generate a first input signal, outputs the first input signal to an SCPA for I codes. The distortion compensation unit compensates, with one of the plurality of correction coefficients for Q codes, distortion of a Q code of the transmission signal to generate a second input signal, and outputs the second input signal to an SCPA for Q codes.

Abstract translation: 存储单元存储包括用于I代码的多个校正系数的第一查找表，并且存储包括用于Q代码的多个校正系数的第二查找表。 I代码的校正系数和Q代码的校正系数的每一个都是复数。 失真补偿单元利用I个代码的多个校正系数中的一个补偿发送信号的I码的失真以产生第一输入信号，将第一输入信号输出给SCPA用于I代码。 失真补偿单元用Q代码的多个校正系数中的一个补偿发送信号的Q码的失真，以产生第二输入信号，并将第二输入信号输出给SCP代码。

公开(公告)号：US09438281B2

公开(公告)日：2016-09-06

申请号：US14655156

申请日：2013-11-29

Applicant: Panasonic Corporation

Inventor： Yoshito Hirai ,  Kouji Okamoto

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B1/04 ,  H03F1/32 ,  H03F3/24

CPC classification number: H04B1/0475 ,  H03F1/3241 ,  H03F1/3247 ,  H03F1/3288 ,  H03F3/24 ,  H03F2201/3233 ,  H04B1/04 ,  H04B2001/0425

Abstract: Disclosed is a distortion compensation apparatus that, by appropriately generating a distortion-compensation coefficient, makes it possible to obtain a desired transmission output, and substantially reduce the amount of power leakage to an adjacent channel. Reception section (103) of the distortion compensation apparatus acquires and demodulates a transmission signal to generate a demodulation signal. Delay adjustment section (104) computes the delay amount of the demodulation signal with respect to the baseband signal, eliminates the delay of the demodulation signal with respect to the baseband signal based on the delay amount, and outputs the baseband signal and the demodulation signal in which the delay is eliminated. Distortion compensation section (101) determines a distortion compensation coefficient in an adaptive digital predistortion process based on the baseband signal and the demodulation signal output by delay adjustment section (104), and multiplies the input signal by the distortion compensation coefficient.

Abstract translation: 公开了一种失真补偿装置，其通过适当地产生失真补偿系数，使得可以获得期望的发送输出，并且基本上减少对相邻信道的电力泄漏量。 失真补偿装置的接收部（103）获取并解调发送信号，生成解调信号。 延迟调整部（104）根据基带信号计算解调信号的延迟量，基于延迟量消除相对于基带信号的解调信号的延迟，并将基带信号和解调信号输出 延迟被消除。 失真补偿部（101）根据由延迟调整部（104）输出的基带信号和解调信号，确定自适应数字预失真处理中的失真补偿系数，并将输入信号乘以失真补偿系数。

公开(公告)号：US08564362B2

公开(公告)日：2013-10-22

申请号：US13759740

申请日：2013-02-05

Applicant: Panasonic Corporation

Inventor： Michiko Tokumaru ,  Heiji Ikoma ,  Kouji Okamoto

IPC: H03K5/00

CPC classification number: H03H11/04 ,  H03H17/0223 ,  H03H2017/0247 ,  H04L25/02 ,  H04L27/36 ,  H04L27/38 ,  H04L27/3845

Abstract: A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Abstract translation: 滤波电路包括两个并行数字滤波器，DAC和LPF。 DAC包括两个并行解码器，并行转换器，开关驱动器和开关。 PLL电路为DAC提供参考时钟。 DAC中提供的分频器将参考时钟的频率除以2，并将半频时钟提供给DAC和两个数字滤波器的并行处理部分（两个解码器和并行到串行转换器）。 这样可以很容易地确保定时裕度，从而允许在几GHz数量级的高速通信中使用。

公开(公告)号：US08912740B2

公开(公告)日：2014-12-16

申请号：US13929982

申请日：2013-06-28

Applicant: Panasonic Corporation

Inventor： Akira Kawabe ,  Kouji Okamoto ,  Fumiaki Senoue ,  Hitoshi Kobayashi ,  Kiyotaka Tanimoto ,  Hideki Nishino ,  Shiro Sakiyama ,  Takashi Morie ,  Akio Yokoyama

IPC: H02P6/16 ,  H02P7/00 ,  G11B5/55 ,  G11B5/596 ,  G11B21/08 ,  G11B21/10 ,  H02P7/29 ,  H02P25/02

CPC classification number: H02P7/00 ,  G11B5/5526 ,  G11B5/59622 ,  G11B21/083 ,  G11B21/106 ,  H02P7/04 ,  H02P7/29 ,  H02P25/028 ,  H02P25/034

Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ΔΣ A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ΔΣ A/D converters to feed back the digital signal to the digital filter.

Abstract translation: 致动器驱动器包括：数字滤波器，被配置为使用反馈数字信号执行数字转矩指令信号的相位补偿; 数字PWM发生器，被配置为响应于所述数字滤波器的输出而产生多个脉冲宽度调制的PWM控制信号; 至少一个H桥，被配置为响应于所述多个PWM控制信号来选择和输出第一或第二端电压; 连续第一连续时间＆ A / D转换器被配置为分别将第一和第二端子电压从模拟转换成数字; 以及反馈滤波器，被配置为对所述第一连续时间和所述第二连续时间Dgr的输出进行抽取; A / D转换器将数字信号反馈到数字滤波器。

公开(公告)号：US09531332B2

公开(公告)日：2016-12-27

申请号：US14655217

申请日：2013-11-29

Applicant: Panasonic Corporation

Inventor： Yoshito Hirai ,  Kouji Okamoto

IPC: H03F1/26 ,  H03F1/32 ,  H03F3/19 ,  H03F3/24 ,  H04B1/04 ,  H03F3/189

CPC classification number: H03F1/3247 ,  H03F1/3241 ,  H03F3/189 ,  H03F3/19 ,  H03F3/24 ,  H03F2200/451 ,  H03F2201/3224 ,  H04B1/0475 ,  H04B2001/0425

Abstract: Disclosed is a distortion-compensation apparatus that can reduce the storage space for storing coefficients required for distortion-compensation calculation, and can accurately execute distortion compensation. Distortion-compensation apparatus (100) compensates for distortion of an output signal from a predetermined circuit by predistortion in which an input signal is preliminarily multiplied by a coefficient. First multiplication section (200c) of distortion-compensation apparatus (100) multiplies an input signal by a first coefficient selected from coefficient candidates in accordance with the input signal; second multiplication section (201c1 to 201cm) multiplies a delay signal of an input signal by a tap coefficient; and adding section (202) outputs a signal obtained by adding together an input signal multiplied by the compensation coefficient and the delay signal multiplied by the tap coefficient to the predetermined circuit.

Abstract translation: 公开了一种失真补偿装置，其可以减少用于存储失真补偿计算所需的系数的存储空间，并且可以精确地执行失真补偿。 失真补偿装置（100）通过预输入信号预先乘以系数的预失真来补偿来自预定电路的输出信号的失真。 失真补偿装置（100）的第一乘法部（200c）根据输入信号将输入信号乘以从系数候选中选择的第一系数; 第二乘法部分（201c1至201cm）将输入信号的延迟信号乘以抽头系数; 和加法部分（202）输出通过将乘以补偿系数的输入信号和乘以抽头系数的延迟信号相加到预定电路而获得的信号。