公开(公告)号：US10237561B2

公开(公告)日：2019-03-19

申请号：US15690645

申请日：2017-08-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Arakawa ,  Kiyofumi Abe ,  Kazuhito Kimura ,  Hideyuki Ohgose ,  Koji Arimura ,  Kazuma Sakakibara

IPC: H04N19/159 ,  H04N19/176 ,  H04N19/119 ,  H04N19/107

Abstract: A video coding apparatus is a video coding apparatus which codes a coding target video based on a coding standard, and includes: a dividing unit which divides an image included in the coding target video into a plurality of control blocks; and a prediction image generating unit which divides each of the control blocks into a plurality of prediction blocks, and generates, for each of the prediction blocks, a prediction image using one of inter prediction and intra prediction, wherein the coding standard allows each of the control blocks to be divided into the prediction blocks such that the prediction blocks have different sizes, and the prediction image generating unit divides each of the control blocks into the prediction blocks such that the prediction blocks all have an identical size, rather than dividing each of the control blocks into the prediction blocks such that the prediction blocks have different sizes.

公开(公告)号：US09723326B2

公开(公告)日：2017-08-01

申请号：US14619993

申请日：2015-02-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kazuma Sakakibara ,  Kiyofumi Abe ,  Naoki Yoshimatsu ,  Hideyuki Ohgose ,  Koji Arimura ,  Hiroshi Arakawa ,  Kazuhito Kimura

IPC: H04N19/61 ,  H04N19/593

CPC classification number: H04N19/103 ,  H04N19/124 ,  H04N19/593 ,  H04N19/61

Abstract: An image encoding method includes: selecting, for each processing block, one of intra prediction modes specified by a coding standard, and performing intra prediction according to the intra prediction mode, wherein the intra prediction modes include a lower-left reference mode in which a processing block located at lower left of a current processing block is referred to, the processing blocks include a first processing block and a second processing block located at upper right of the first processing block, the second processing block being equal in size to the first processing block, the coding standard defines that information on the second processing block is written into a bitstream after information on the first processing block, and in the intra prediction, (i) selection of the lower-left reference mode is prohibited and intra prediction is performed on the second processing block, and, (ii) intra prediction is performed on the first processing block.

公开(公告)号：US10038901B2

公开(公告)日：2018-07-31

申请号：US15631755

申请日：2017-06-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kazuma Sakakibara ,  Kiyofumi Abe ,  Naoki Yoshimatsu ,  Hideyuki Ohgose ,  Koji Arimura ,  Hiroshi Arakawa ,  Kazuhito Kimura

IPC: H04N19/61 ,  H04N19/103 ,  H04N19/124 ,  H04N19/593

CPC classification number: H04N19/103 ,  H04N19/124 ,  H04N19/593 ,  H04N19/61

Abstract: An image encoding method includes: selecting, for each processing block, one of intra prediction modes specified by a coding standard, and performing intra prediction according to the intra prediction mode, wherein the intra prediction modes include a lower-left reference mode in which a processing block located at lower left of a current processing block is referred to, the processing blocks include a first processing block and a second processing block located at upper right of the first processing block, the second processing block being equal in size to the first processing block, the coding standard defines that information on the second processing block is written into a bitstream after information on the first processing block.

公开(公告)号：US09781434B2

公开(公告)日：2017-10-03

申请号：US14611871

申请日：2015-02-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Arakawa ,  Kiyofumi Abe ,  Kazuhito Kimura ,  Hideyuki Ohgose ,  Koji Arimura ,  Kazuma Sakakibara

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/119 ,  H04N19/107 ,  H04N19/70

CPC classification number: H04N19/159 ,  H04N19/107 ,  H04N19/119 ,  H04N19/176

Abstract: A video coding apparatus is a video coding apparatus which codes a coding target video based on a coding standard, and includes: a dividing unit which divides an image included in the coding target video into a plurality of control blocks; and a prediction image generating unit which divides each of the control blocks into a plurality of prediction blocks, and generates, for each of the prediction blocks, a prediction image using one of inter prediction and intra prediction, wherein the coding standard allows each of the control blocks to be divided into the prediction blocks such that the prediction blocks have different sizes, and the prediction image generating unit divides each of the control blocks into the prediction blocks such that the prediction blocks all have an identical size, rather than dividing each of the control blocks into the prediction blocks such that the prediction blocks have different sizes.

公开(公告)号：US10225576B2

公开(公告)日：2019-03-05

申请号：US14641086

申请日：2015-03-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kiyofumi Abe ,  Kazuhito Kimura ,  Hideyuki Ohgose ,  Hiroshi Arakawa ,  Koji Arimura ,  Kazuma Sakakibara

IPC: H04N19/61 ,  H04N19/593 ,  H04N19/51 ,  H04N19/124

Abstract: A video coding apparatus including a dividing part that outputs the coding target picture divided for each coding unit (basic CU); a prediction processor that generates a prediction image by performing one of intra prediction and inter-screen prediction; a difference calculator that generates a difference image by calculating a difference between the generated prediction image and an image corresponding to the prediction image in the coding target picture; a residual coder that generates a residual coefficient by performing transform processing and quantization processing on the generated difference image; an integration unit that integrates a plurality of basic CUs included in an N×N-pixel region into one new CU, and a code string generator that generates a code string corresponding to the post-integration new CU by performing variable-length coding and arithmetic coding on coding information and the residual coefficient.

公开(公告)号：US09866841B2

公开(公告)日：2018-01-09

申请号：US14800643

申请日：2015-07-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yuki Maruyama ,  Kiyofumi Abe ,  Hideyuki Ohgose ,  Koji Arimura ,  Hiroshi Arakawa ,  Kazuma Sakakibara ,  Kazuhito Kimura

IPC: H04N19/159 ,  H04N19/186 ,  H04N19/11

CPC classification number: H04N19/159 ,  H04N19/11 ,  H04N19/186

Abstract: Provided is an image coding method which obtains a picture, and codes the obtained picture. The image coding method generates a processing block, performs a first intra prediction that selects one intra prediction mode from a first set of candidates based on a component of a first signal contained in the processing block, performs a second intra prediction that selects one intra prediction mode from a second set of candidates based on a component of a second signal contained in the processing block. The first set of candidates includes a plurality of intra prediction modes, and the second set of candidates includes an intra prediction mode, having no dependency between the second intra prediction and the first intra prediction, of the plurality of intra prediction modes. The first intra prediction and the second intra prediction are performed in parallel.

公开(公告)号：US09473787B2

公开(公告)日：2016-10-18

申请号：US14660419

申请日：2015-03-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Koji Arimura ,  Kazuhito Kimura ,  Hideyuki Ohgose ,  Hiroshi Arakawa ,  Kiyofumi Abe ,  Kazuma Sakakibara

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/513 ,  H04N19/56 ,  H04N19/172 ,  H04N19/176

CPC classification number: H04N19/513 ,  H04N19/105 ,  H04N19/119 ,  H04N19/149 ,  H04N19/172 ,  H04N19/176 ,  H04N19/56

Abstract: In an exemplary embodiment, in order to avoid enlargement of a circuit scale to perform coding processing in real time, a block size of a PU (evaluation PU (Prediction Unit)) used to evaluate a merge mode is restricted and the number of evaluation target merge candidates is restricted. In the case where the evaluation PU has the block size in which a CU (Cording Unit) is divided, at least one merge candidate common to a merge candidate list of a PU (inclusion PU) having the block size including the evaluation PU and a merge candidate list of each of a plurality of evaluation PUs is selected as the evaluation target merge candidate from the merge candidate lists of the evaluation PUs. In performing cost evaluation processing for the evaluation PU, cost evaluation processing is simultaneously performed on the inclusion PU using a calculated prediction residual.

Abstract translation: 在一个示例性实施例中，为了避免放大电路规模以实时执行编码处理，用于评估合并模式的PU（评估PU（预测单元））的块大小被限制，并且评估目标的数量 合并候选人受到限制。 在评价PU具有划分CU（Cording Unit）的块大小的情况下，具有包含评估PU的块大小的PU（包含PU）的合并候选列表的公共的至少一个合并候选和 从评估PU的合并候选列表中选择多个评估PU中的每一个的合并候选列表作为评估对象合并候选。 在进行评价用PU的成本评价处理中，使用计算出的预测残差，对包含PU同时进行成本评价处理。