公开(公告)号：US20250140470A1

公开(公告)日：2025-05-01

申请号：US18834498

申请日：2022-12-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hong-An SHIH ,  Kenichi ASANUMA ,  Koji TAKAHASHI

IPC: H01F27/29 ,  H01F3/08 ,  H01F5/04 ,  H02M3/155

Abstract: A coupled inductor includes: a magnetic body; a first conductor provided at least partially inside the magnetic body; and a second conductor provided at least partially inside the magnetic body and coupled to the first conductor. The magnetic body includes: a first surface and a second surface facing away from each other; and a third surface and a fourth surface facing away from each other and orthogonal to the first surface and the second surface. The first conductor includes: a first terminal provided at the first surface; and a second terminal provided at the second surface. The second conductor includes: a third terminal provided at the third surface; and a fourth terminal provided at the fourth surface.

公开(公告)号：US20240048139A1

公开(公告)日：2024-02-08

申请号：US18264556

申请日：2021-10-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Koji TAKAHASHI ,  Manabu YANAGIHARA ,  Noboru NEGORO ,  Takeshi AZUMA

IPC: H03K17/30 ,  H03K17/0412 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K17/302 ,  H03K17/04123 ,  H03K19/0013 ,  H03K19/00361

Abstract: A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate includes: a first terminal to which a gate control signal is input; a gate signal line connecting the first terminal and the first gate; a resistance element inserted in the gate signal line; a capacitance element connected in parallel with the resistance element; a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period.

公开(公告)号：US20220139797A1

公开(公告)日：2022-05-05

申请号：US17431657

申请日：2020-01-14

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Koji TAKAHASHI ,  Kazuhiro YAHATA ,  Yoshihisa MINAMI ,  Hiroki AKASHI ,  Shinya MIYAZAKI

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: The semiconductor module includes: a heat dissipation board including first to third wiring patterns; a first metal plate on the first wiring pattern, a second metal plate on the second wiring pattern, a first semiconductor chip and a first intermediate board which are on the first metal plate, a second semiconductor chip and a second intermediate board which are on the second metal plate. A first metal film on the first intermediate board is electrically connected to the first semiconductor chip and the second metal plate, and a second metal film on the second intermediate board is electrically connected to the second semiconductor chip and the third wiring pattern.