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公开(公告)号：US20170194524A1
公开(公告)日：2017-07-06
申请号：US15364556
申请日：2016-11-30
Inventor： Satoshi Tohoda , Masato Shigematsu , Kenta Matsuyama
IPC: H01L31/05 , H01L31/0376 , H01L31/0352 , H01L31/044
CPC classification number: H01L31/022441 , H01L31/0747 , H01L31/1804 , Y02E10/547 , Y02P70/521
Abstract: Provided is a solar cell that can suppress loss of power generation performance of a solar cell module when shaded and a solar cell module having the solar cell. An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.
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公开(公告)号：US20170179315A1
公开(公告)日：2017-06-22
申请号：US15393870
申请日：2016-12-29
Inventor： Satoshi Tohoda , Masato Shigematsu , Kenta Matsuyama
IPC: H01L31/0376 , H01L31/0443 , H01L31/18 , H01L31/05
CPC classification number: H01L31/1804 , H01L31/022441 , H01L31/0747 , Y02E10/547 , Y02P70/521
Abstract: An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.
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公开(公告)号：USD894824S1
公开(公告)日：2020-09-01
申请号：US29658454
申请日：2018-07-31
Designer： Naoki Yoshimura , Keiichiro Masuko , Daisuke Fujishima , Masato Shigematsu
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公开(公告)号：US10014420B2
公开(公告)日：2018-07-03
申请号：US15220394
申请日：2016-07-27
Inventor： Masato Shigematsu , Naofumi Hayashi
IPC: H01L31/00 , H01L31/0224 , H01L31/0747 , H01L31/20 , H01L31/18 , H01L31/075
CPC classification number: H01L31/022441 , H01L31/0747 , H01L31/075 , H01L31/1804 , H01L31/20 , Y02E10/547 , Y02P70/521
Abstract: A solar cell includes: a semiconductor substrate having a light-receiving surface and a back surface; a first-conductivity-type first semiconductor layer on the back surface; a second-conductivity-type second semiconductor layer on the back surface; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; and an insulating layer in a boundary region between a first-conductivity-type region of the first semiconductor layer and a second-conductivity-type region of the second semiconductor layer. The insulating layer has an inclined side surface adjacent the second-conductivity-type region inclined such that the thickness of the insulating layer decreases with decreasing distance from the second-conductivity-type region. The width of the inclined surface in a direction perpendicular to the thickness direction of the insulating layer and toward the second-conductivity-type region is 10 to 300 times the thickness of the insulating layer in a region excluding the inclined surface.
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Patent Agency Ranking
公开(公告)号：USD828292S1
公开(公告)日：2018-09-11
申请号：US29588350
申请日：2016-12-20
Designer： Naoki Yoshimura , Keiichiro Masuko , Daisuke Fujishima , Masato Shigematsu
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公开(公告)号：US10923610B2
公开(公告)日：2021-02-16
申请号：US15364556
申请日：2016-11-30
Inventor： Satoshi Tohoda , Masato Shigematsu , Kenta Matsuyama
IPC: H01L31/0747 , H01L31/0224 , H01L31/18
Abstract: Provided is a solar cell that can suppress loss of power generation performance of a solar cell module when shaded and a solar cell module having the solar cell. An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.
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公开(公告)号：US10784396B2
公开(公告)日：2020-09-22
申请号：US15393870
申请日：2016-12-29
Inventor： Satoshi Tohoda , Masato Shigematsu , Kenta Matsuyama
IPC: H01L31/0747 , H01L31/18 , H01L31/0224
Abstract: An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.
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公开(公告)号：USD894823S1
公开(公告)日：2020-09-01
申请号：US29658451
申请日：2018-07-31
Designer： Naoki Yoshimura , Keiichiro Masuko , Daisuke Fujishima , Masato Shigematsu
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公开(公告)号：US09705027B2
公开(公告)日：2017-07-11
申请号：US15164874
申请日：2016-05-26
Inventor： Naofumi Hayashi , Mitsuaki Morigami , Masato Shigematsu , Takahiro Mishima
IPC: H01L21/00 , H01L31/20 , H01L31/0747 , H01L31/0224 , H01L31/18
CPC classification number: H01L31/202 , H01L31/022441 , H01L31/022491 , H01L31/0747 , H01L31/1804 , Y02E10/547 , Y02P70/521
Abstract: A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.
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