公开(公告)号：US20170221814A1

公开(公告)日：2017-08-03

申请号：US15329464

申请日：2015-07-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Satoshi TAMURA

IPC: H01L23/522 ,  H01L23/13 ,  H01L27/088 ,  H01L25/065 ,  H01L23/535

Abstract: A semiconductor device includes: a high-side transistor having a first gate electrode, first drain electrodes and first source electrodes; a low-side transistor having a second gate electrode, second drain electrodes and second source electrodes; a plurality of first drain pads that are disposed above the first drain electrodes and are electrically connected to the first drain electrodes; a plurality of first source pads that are disposed above the second source electrodes and are electrically connected to the second source electrodes; a plurality of first common interconnects that are disposed above the first source electrodes and above the second drain electrodes and are electrically connected to the first source electrodes and the second drain electrodes; and a plurality of second common interconnects that are connected to the first common interconnects, and extend in a direction that intersects with the first common interconnects.

公开(公告)号：US20210057564A1

公开(公告)日：2021-02-25

申请号：US17091302

申请日：2020-11-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu UMEDA ,  Kazuhiro KAIBARA ,  Satoshi TAMURA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20 ,  H01L29/06

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

公开(公告)号：US20180145166A1

公开(公告)日：2018-05-24

申请号：US15873438

申请日：2018-01-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu UMEDA ,  Kazuhiro KAIBARA ,  Satoshi TAMURA

IPC: H01L29/78 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/78 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/10 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7786

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.