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公开(公告)号：US20230412153A1
公开(公告)日：2023-12-21
申请号：US18461119
申请日：2023-09-05
Inventor： Yusuke KINOSHITA , Takashi ICHIRYU , Hidetoshi ISHIDA
Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
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公开(公告)号：US20230145803A1
公开(公告)日：2023-05-11
申请号：US17916743
申请日：2021-04-05
Inventor： Ryosuke MAEDA , Yusuke KINOSHITA , Hidetoshi ISHIDA
CPC classification number: H03K17/166 , H02H3/202
Abstract: A control circuit controls a switching element including a gate and a source corresponding to the gate. The control circuit includes an inductor, a circuit element, and a resistor. The inductor is connected between the gate and the source of the switching element. The circuit element is connected in series to the inductor between the gate and the source. The circuit element allows an electric current to flow therethrough in response to generation of electromotive force in the inductor. The resistor is connected in parallel to the inductor and the circuit element between the gate and the source.
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公开(公告)号：US20210265993A1
公开(公告)日：2021-08-26
申请号：US17256642
申请日：2019-06-12
Inventor： Yusuke KINOSHITA , Yasuhiro YAMADA , Hidekazu UMEDA
IPC: H03K17/56 , H01L29/20 , H01L29/205 , H01L29/778 , H02M7/537
Abstract: A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.
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公开(公告)号：US20200027814A1
公开(公告)日：2020-01-23
申请号：US16497744
申请日：2018-03-27
Inventor： Takashi ICHIRYU , Masanori NOMURA , Yusuke KINOSHITA , Hidetoshi ISHIDA , Yasuhiro YAMADA
IPC: H01L23/367 , H01L23/373 , H01L23/29 , H01L23/00 , H01L23/31 , H01L23/532
Abstract: A semiconductor device includes a supporting substrate, a semiconductor chip, a resin member, and a heat-dissipating metal layer. The supporting substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the supporting substrate. The semiconductor chip includes a plurality of electrodes. The semiconductor chip is bonded to the supporting substrate on one side thereof with the first surface. The resin member has a first surface and a second surface located opposite from each other in a thickness direction defined for the resin member. The resin member covers at least a side surface of the supporting substrate and a side surface of the semiconductor chip. The heat-dissipating metal layer is arranged in contact with the supporting substrate and the resin member to cover the second surface of the supporting substrate and the second surface of the resin member at least partially.
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公开(公告)号：US20170221814A1
公开(公告)日：2017-08-03
申请号：US15329464
申请日：2015-07-01
Inventor： Yusuke KINOSHITA , Satoshi TAMURA
IPC: H01L23/522 , H01L23/13 , H01L27/088 , H01L25/065 , H01L23/535
Abstract: A semiconductor device includes: a high-side transistor having a first gate electrode, first drain electrodes and first source electrodes; a low-side transistor having a second gate electrode, second drain electrodes and second source electrodes; a plurality of first drain pads that are disposed above the first drain electrodes and are electrically connected to the first drain electrodes; a plurality of first source pads that are disposed above the second source electrodes and are electrically connected to the second source electrodes; a plurality of first common interconnects that are disposed above the first source electrodes and above the second drain electrodes and are electrically connected to the first source electrodes and the second drain electrodes; and a plurality of second common interconnects that are connected to the first common interconnects, and extend in a direction that intersects with the first common interconnects.
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Patent Agency Ranking
公开(公告)号：US20240259018A1
公开(公告)日：2024-08-01
申请号：US18563242
申请日：2022-03-24
Inventor： Yusuke KINOSHITA , Ryosuke MAEDA , Satoshi NAKAZAWA
IPC: H03K17/687
CPC classification number: H03K17/6871
Abstract: In a switch system, a voltage clamping element is connected to a semiconductor switch in parallel. An active clamping circuit is connected between a control terminal and a first main terminal of the semiconductor switch. The active clamping circuit includes a first diode, a second diode, and a control switch. A second anode of the second diode is connected to a first anode of the first diode. The control switch is connected between the first anode of the first diode and the control terminal of the semiconductor switch. A second control unit controls the control switch. A breakdown voltage of the first diode is smaller than a clamp voltage of the voltage clamping element.
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公开(公告)号：US20230412154A1
公开(公告)日：2023-12-21
申请号：US18461126
申请日：2023-09-05
Inventor： Yusuke KINOSHITA , Takashi ICHIRYU , Hidetoshi ISHIDA
Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
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公开(公告)号：US20220271738A1
公开(公告)日：2022-08-25
申请号：US17626296
申请日：2020-07-10
Inventor： Yusuke KINOSHITA , Takashi ICHIRYU , Hidetoshi ISHIDA
Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
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公开(公告)号：US20220224321A1
公开(公告)日：2022-07-14
申请号：US17614716
申请日：2020-04-28
Inventor： Yusuke KINOSHITA , Takashi ICHIRYU , Ryusuke KANOMATA , Hidetoshi ISHIDA
IPC: H03K17/04
Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.
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公开(公告)号：US20210408934A1
公开(公告)日：2021-12-30
申请号：US17290489
申请日：2019-08-23
Inventor： Yusuke KINOSHITA , Yasuhiro YAMADA , Takashi ICHIRYU , Masanori NOMURA , Hidetoshi ISHIDA
IPC: H02M7/483 , H02M1/08 , H01L29/778
Abstract: A GaN layer is formed over the substrate. An AlGaN layer is formed on the GaN layer. A first source electrode, a first gate electrode, a second gate electrode, and a second source electrode are formed on or over the AlGaN layer. A first p-type Alx1Ga1-x1N layer where 0≤x1
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