公开(公告)号：US20210057564A1

公开(公告)日：2021-02-25

申请号：US17091302

申请日：2020-11-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu UMEDA ,  Kazuhiro KAIBARA ,  Satoshi TAMURA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20 ,  H01L29/06

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

公开(公告)号：US20180145166A1

公开(公告)日：2018-05-24

申请号：US15873438

申请日：2018-01-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu UMEDA ,  Kazuhiro KAIBARA ,  Satoshi TAMURA

IPC: H01L29/78 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/78 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/10 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7786

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

公开(公告)号：US20210265993A1

公开(公告)日：2021-08-26

申请号：US17256642

申请日：2019-06-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Yasuhiro YAMADA ,  Hidekazu UMEDA

IPC: H03K17/56 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H02M7/537

Abstract: A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

公开(公告)号：US20230260959A1

公开(公告)日：2023-08-17

申请号：US18140206

申请日：2023-04-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tetsushi KONDA ,  Kenji KITAMURA ,  Takahito HAGIWARA ,  Ryo MATSUBAYASHI ,  Hidekazu UMEDA

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L2224/8384 ,  H01L23/3121

Abstract: A method for manufacturing a composite structure includes: an application step including providing a bonding material on a base member by applying a metal paste onto the base member; a preheating step including heating the bonding material before an element to be bonded is stacked on the bonding material and thereby drying the bonding material until a percentage of an organic component in the bonding material becomes 3% by mass and equal to or less than 8% by mass with respect to the bonding material; a mounting step including stacking the element to be bonded onto the bonding material and heating the bonding material to form a multi-layer stack; and a sintering step including sintering the bonding material by heating the multi-layer stack in a heating furnace and thereby forming the bonding layer.