公开(公告)号：US20180351208A1

公开(公告)日：2018-12-06

申请号：US16100586

申请日：2018-08-10

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Satoshi SHIBATA ,  Yu NISHITANI ,  Takuji TSUJITA

IPC: H01M10/0562 ,  C23C16/455 ,  H01M10/054

CPC classification number: H01M10/0562 ,  C23C16/308 ,  C23C16/45531 ,  C23C16/45555 ,  C23C16/45561 ,  H01M10/054 ,  H01M2300/0071

Abstract: A solid electrolyte includes an oxynitride that contains an alkaline-earth metal, phosphorus, oxygen, and nitrogen. A P2p spectrum obtained by an X-ray photoelectron spectroscopy measurement of the oxynitride contains a peak component originating from a P—N bond.

公开(公告)号：US20160341613A1

公开(公告)日：2016-11-24

申请号：US15229778

申请日：2016-08-05

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Michihito UEDA ,  Yukihiro KANEKO ,  Yu NISHITANI ,  Atsushi OMOTE

IPC: G01L5/00 ,  G01L1/22 ,  G01L1/18

CPC classification number: G01L5/0052 ,  G01L1/18 ,  G01L1/2293

Abstract: The present invention provides a shock recording device, comprising: a vibration energy harvester comprising a first electrode and a second electrode, the vibration energy harvester converting an energy of a shock applied thereto into a potential difference between the first electrode and the second electrode; and a ferroelectric transistor comprising a gate electrode, a source electrode, and a drain electrode, the ferroelectric transistor further comprising a stacked structure of a ferroelectric layer and a semiconductor layer. The gate electrode is electrically connected to the first electrode. The source electrode is electrically connected to the second electrode. This shock recording device does not need a power source used to record a shock.

公开(公告)号：US20250089580A1

公开(公告)日：2025-03-13

申请号：US18954969

申请日：2024-11-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Asami NISHIKAWA ,  Satoshi SHIBATA ,  Yu NISHITANI ,  Tetsuya ASANO ,  Takuji TSUJITA ,  Yuta SUGIMOTO

IPC: H10N70/20 ,  G01R27/14 ,  H10B63/00 ,  H10N70/00

Abstract: An interconnect structure includes: an interconnect layer containing a metal element as a main component and extending in a direction; a metal layer opposite to the interconnect layer, and a solid electrolyte layer between the interconnect layer and the metal layer. The solid electrolyte layer encloses the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction. The interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer.

公开(公告)号：US20210050513A1

公开(公告)日：2021-02-18

申请号：US17007382

申请日：2020-08-31

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Asami NISHIKAWA ,  Satoshi SHIBATA ,  Yu NISHITANI ,  Tetsuya ASANO ,  Takuji TSUJITA ,  Yuta SUGIMOTO

IPC: H01L45/00 ,  H01L27/24 ,  G01R27/14

Abstract: An interconnect structure according to the present disclosure includes: an interconnect layer containing a metal element as a main component and extending in a direction; a metal layer opposite to the interconnect layer, and a solid electrolyte layer between the interconnect layer and the metal layer. The solid electrolyte layer encloses the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction. The interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer.

公开(公告)号：US20150178619A1

公开(公告)日：2015-06-25

申请号：US14611145

申请日：2015-01-30

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yu NISHITANI ,  Yukihiro KANEKO ,  Michihito UEDA

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: In a neural network circuit element, a neuron circuit includes a waveform generating circuit for generating an analog pulse voltage, and a switching pulse voltage which is input as a first input signal to another neural network circuit element; a synapse circuit is configured such that the analog pulse voltage generated in the neuron circuit of the neural network circuit element including the synapse circuit is input to a third terminal of a variable resistance element of the synapse circuit, for a permissible input period, in the first input signal from another neural network circuit element; and the synapse circuit is configured such that the resistance value of the variable resistance element is changed in response to an electric potential difference between a first terminal and the third terminal, which occurs depending on a magnitude of the analog pulse voltage for the permissible input period.

Abstract translation: 在神经网络电路元件中，神经元电路包括用于产生模拟脉冲电压的波形发生电路和作为第一输入信号输入到另一个神经网络电路元件的开关脉冲电压; 突触电路被配置为使得包括突触电路的神经网络电路元件的神经元电路中产生的模拟脉冲电压在允许的输入周期中被输入到突触电路的可变电阻元件的第三端子 来自另一神经网络电路元件的第一输入信号; 并且突触电路被配置为使得可变电阻元件的电阻值响应于第一端子和第三端子之间的电位差而改变，这取决于在允许输入周期的模拟脉冲电压的大小 。