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公开(公告)号：US07386775B2
公开(公告)日：2008-06-10
申请号：US11206846
申请日：2005-08-18
CPC分类号： G01R31/318583
摘要： Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.
摘要翻译： 公开了用于待测仿真设备（'DUT'）的扫描验证的方法，装置和产品，DUT具有扫描链，扫描输入和扫描输出，其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始，验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播，验证从扫描链的末端输出到扫描输出的正确数据，并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。
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公开(公告)号：US20070061644A1
公开(公告)日：2007-03-15
申请号：US11206846
申请日：2005-08-18
IPC分类号： G01R31/28
CPC分类号： G01R31/318583
摘要： Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.
摘要翻译： 公开了用于待测仿真设备（'DUT'）的扫描验证的方法，装置和产品，DUT具有扫描链，扫描输入和扫描输出，其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始，验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播，验证从扫描链的末端输出到扫描输出的正确数据，并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。
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公开(公告)号：US20080195339A1
公开(公告)日：2008-08-14
申请号：US12102510
申请日：2008-04-14
IPC分类号： G01R31/00
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译： 公开了一种用于进行时间检查的装置。 用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。 在测试期间，信号记录器耦合到被测设备（DUT）。 每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。 每个计数模块与边缘检测模块之一相关联。 每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。 在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。
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公开(公告)号：US20070136703A1
公开(公告)日：2007-06-14
申请号：US11297308
申请日：2005-12-08
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译： 公开了一种用于进行时间检查的装置。 用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。 在测试期间，信号记录器耦合到被测设备（DUT）。 每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。 每个计数模块与边缘检测模块之一相关联。 每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。 在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。
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公开(公告)号：US07853420B2
公开(公告)日：2010-12-14
申请号：US12102510
申请日：2008-04-14
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译： 公开了一种用于进行时间检查的装置。 用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。 在测试期间，信号记录器耦合到被测设备（DUT）。 每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。 每个计数模块与边缘检测模块之一相关联。 每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。 在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。
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公开(公告)号：US07464354B2
公开(公告)日：2008-12-09
申请号：US11297308
申请日：2005-12-08
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译： 公开了一种用于进行时间检查的装置。 用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。 在测试期间，信号记录器耦合到被测设备（DUT）。 每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。 每个计数模块与边缘检测模块之一相关联。 每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。 在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。
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公开(公告)号：US20080195340A1
公开(公告)日：2008-08-14
申请号：US12102525
申请日：2008-04-14
IPC分类号： G01R31/00
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译： 公开了一种用于进行时间检查的装置。 用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。 在测试期间，信号记录器耦合到被测设备（DUT）。 每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。 每个计数模块与边缘检测模块之一相关联。 每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。 在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。
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8.发明申请System and Method for Reducing Test Time for Loading and Executing an Architecture Verification Program for a Soc 失效系统和方法，用于减少加载和执行体系结构验证程序的测试时间公开(公告)号：US20080034261A1
公开(公告)日：2008-02-07
申请号：US11457538
申请日：2006-07-14
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.
摘要翻译： 提供了一种用于减少用于加载和执行系统级芯片（SoC）的架构验证程序的测试时间的系统和方法。 说明性实施例的机制重新组织SoC的扫描链，并提供用于组织和流水线架构验证程序（AVP）数据的算法，用于扫描重组的扫描链。 扫描链被重组，以便对齐用于多个扫描链中的每个存储器阵列的存储器阵列数据的扫描单元。 扫描链进一步重组，使得每个扫描链具有唯一的AVP数据，即，没有扫描链具有多于一个的存储器阵列的信息。 流水线算法根据扫描链的长度，存储器阵列数据的最大大小以及扫描链中存储器阵列的扫描单元的位置来捆绑数据。
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9.发明申请Method and system for generating checkpoints of hardware description language simulations that include a specific model state together with a software testcase state 审中-公开用于生成硬件描述语言模拟的检查点的方法和系统，其包括具体的模型状态以及软件测试用例状态公开(公告)号：US20070220338A1
公开(公告)日：2007-09-20
申请号：US11351233
申请日：2006-02-09
申请人： Parag Birmiwal , Tilman Gloekler , Srinivas Polisetty , Karl Uhl
发明人： Parag Birmiwal , Tilman Gloekler , Srinivas Polisetty , Karl Uhl
IPC分类号： G06F11/00
CPC分类号： G06F17/5022 , G06F11/3672
摘要： A method for performing verification is disclosed. In response to determining that a log replay module operating in a replay mode has received a command from a testcase that is not equal to a next command in a replay log, a determination is made whether the command is a create relay checkpoint command with a testcase parameter matching a model checkpoint file. In response to determining that the command from the testcase is the create replay checkpoint command with the testcase parameter matching the model checkpoint file, the model checkpoint file is loaded into the simulator, and one or more items of cycle information of the simulator are set to information corresponding to the model checkpoint file.
摘要翻译： 公开了一种用于执行验证的方法。 响应于确定以重放模式操作的日志重放模块已经从重放日志中不等于下一个命令的测试用例接收到命令，确定该命令是否是具有测试用例的创建中继检查点命令 参数匹配模型检查点文件。 响应于确定来自测试用例的命令是创建重放检查点命令，其中testcase参数与模型检查点文件匹配，模型检查点文件被加载到模拟器中，并且模拟器的一个或多个循环信息项被设置为 对应于模型检查点文件的信息。
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10.发明授权System and method for reducing test time for loading and executing an architecture verification program for a SoC 失效用于减少加载和执行SoC架构验证程序的测试时间的系统和方法公开(公告)号：US07512925B2
公开(公告)日：2009-03-31
申请号：US11457538
申请日：2006-07-14
CPC分类号： G01R31/318536
摘要： A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.
摘要翻译： 提供了一种用于减少用于加载和执行系统级芯片（SoC）的架构验证程序的测试时间的系统和方法。 说明性实施例的机制重新组织SoC的扫描链，并提供用于组织和流水线架构验证程序（AVP）数据的算法，用于扫描重组的扫描链。 扫描链被重组，以便对齐用于多个扫描链中的每个存储器阵列的存储器阵列数据的扫描单元。 扫描链进一步重组，使得每个扫描链具有唯一的AVP数据，即，没有扫描链具有多于一个的存储器阵列的信息。 流水线算法根据扫描链的长度，存储器阵列数据的最大大小以及扫描链中存储器阵列的扫描单元的位置来捆绑数据。
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