公开(公告)号：US07218699B2

公开(公告)日：2007-05-15

申请号：US11038487

申请日：2005-01-21

Applicant: Jean-Luc De Gouy ,  Pascal Gabet

Inventor： Jean-Luc De Gouy ,  Pascal Gabet

IPC: H03K21/00

CPC classification number: H03K23/544 ,  H03K23/665

Abstract: A divider to divide a frequency Fe comprises at least the following elements: three flip-flop circuits, each of the flip-flop circuits receiving the frequency to be divided, every feedback loop between an output of a flip-flop circuit and its input or the input of the other flip-flop circuits comprising a single multiplexer, wherein one of the flip-flop circuits commands the loading of all the flip-flop circuits during one period of the frequency A multiplexer has two inputs, one selection bit and one output and is integrated into a flip-flop circuit.

Abstract translation: 至少分成以下元件的分频器：三个触发器电路，每个触发器电路接收要被分频的频率，每个反馈回路在 触发器电路及其输入或包括单个多路复用器的其它触发器电路的输入，其中触发器电路中的一个命令在频率A多路复用器具有两个触发器电路的一个周期期间所有触发器电路的加载 输入，一个选择位和一个输出，并被集成到触发器电路中。

公开(公告)号：US06597208B1

公开(公告)日：2003-07-22

申请号：US09926587

申请日：2001-11-21

Applicant: Pascal Gabet ,  Jean-Luc De Gouy

Inventor： Pascal Gabet ,  Jean-Luc De Gouy

IPC: H03D324

CPC classification number: H04L27/122 ,  G06F1/0328 ,  G06F7/72

Abstract: A direct digital frequency-synthesis device includes a modulo-M coherent accumulator that generates a first phase law from a frequency-control word. A table, addressed by a second phase law derived from the first phase law, generates a digital sinusoidal signal. A digital/analog converter converts the digital sinusoidal signal into an analog sinusoidal signal. A filter filters the analog sinusoidal signal. And, a divider divides the filtered signal. The divider has a lower order than M and has a synchronization input driven by a synchronization pulse for re-synchronizing the signal after division, the synchronization pulse being derived from the phase law. Such a device may find particular application to digital synthesizers for radar.

Abstract translation: 直接数字频率合成装置包括模M相干累加器，其从频率控制字产生第一相位定律。 由第一相定律得出的第二相定律寻址的表产生数字正弦信号。 数字/模拟转换器将数字正弦信号转换为模拟正弦信号。 滤波器滤波模拟正弦信号。 并且，除法器分割滤波后的信号。 除法器具有比M更低的阶数，并且具有由同步脉冲驱动的同步输入，用于重新同步分频后的信号，同步脉冲从相位律导出。 这样的装置可以发现用于雷达的数字合成器的特定应用。

公开(公告)号：US06262604B1

公开(公告)日：2001-07-17

申请号：US09339100

申请日：1999-06-24

Applicant: Pascal Gabet ,  Jean-Luc de Gouy

Inventor： Pascal Gabet ,  Jean-Luc de Gouy

IPC: H03B1900

CPC classification number: G06F1/0328

Abstract: A digital frequency synthesizer comprises means for the generation of the samples of a digital signal to be converted into an analog signal encoded on N bits as a function of a frequency control word, means for the generation of a noise signal encoded on N bits, and a digital-analog converter, the useful signal and the noise signal being truncated to M bits before being added up by an adder. The result of the addition is converted into analog signal form by the digital-analog converter. The generated noise has at least a noise density substantially equal to a law of equiprobability, this density being zero outside a given space. Application especially to direct digital synthesis, for example in the field of radar techniques or that of instrumentation.

Abstract translation: 数字频率合成器包括用于产生要转换为以N位编码的模拟信号作为频率控制字的函数的数字信号的采样的装置，用于产生以N位编码的噪声信号的装置，以及 数字模拟转换器，有用信号和噪声信号被加法器相加之前被截断为M位。 加法的结果由数模转换器转换成模拟信号形式。 所产生的噪声至少具有基本上等于等能性定律的噪声密度，该密度在给定空间外为零。 特别适用于直接数字合成，例如在雷达技术领域或仪器领域。

公开(公告)号：US07002380B2

公开(公告)日：2006-02-21

申请号：US10772584

申请日：2004-02-06

Applicant: Jean-Luc De Gouy ,  Pascal Gabet ,  Gilles Neveu

Inventor： Jean-Luc De Gouy ,  Pascal Gabet ,  Gilles Neveu

IPC: H03K21/00

CPC classification number: H03K23/68 ,  H03K23/667 ,  H03L7/193

Abstract: In a frequency divider enabling the division by N of a frequency Fe and comprising at least one prescaler followed by a division chain, the prescaler has at least one input for the frequency signal Fe to be divided, one input for a command NA of the basic division rank of the prescaler and one input for a command ΔNA coming from the division chain and enabling NA to be made to vary by one unit; the division chain comprises at least one division stage (K) comprising at least one divider by 2, giving a divided frequency F(K), a switch controlled by the divider by 2, the switch having one input for a piece of programming data R(K), one input for the carry signal RX(K+1) of the next stage and one output for the carry signal RX(K) for the previous stage. Application to the field of phase-locked loop frequency synthesis.

Abstract translation: 在能够由频率Fe除以N并且包括至少一个预分频器和分割链的分频器中，预分频器具有用于要分频的频率信号Fe的至少一个输入，用于基本信号的命令NA的一个输入 预分频器的分级等级和来自分割链的命令DeltaNA的一个输入，并使NA可以变化一个单位; 该分割链包括至少一个包括至少一个除法器2的分频级（K），给出分频F（K），由除法器控制的开关2，开关具有用于编程数据R的一个输入 （K），下一级的进位信号RX（K + 1）的一个输入和用于前一级的进位信号RX（K）的一个输出。 应用于锁相环频率合成领域。

公开(公告)号：US06388601B1

公开(公告)日：2002-05-14

申请号：US09830150

申请日：2001-04-23

Applicant: Jean-Luc De Gouy ,  Pascal Gabet ,  Philippe Benabes

Inventor： Jean-Luc De Gouy ,  Pascal Gabet ,  Philippe Benabes

IPC: H03M112

CPC classification number: H03M3/37 ,  H03M3/458

Abstract: A sigma-delta modulator having a propagation delay &Dgr;t between an input of an analog-to-digital converter and an output of the digital-to-analog converter. A subtractor is located in a direct chain between an amplification unit and the analog-to-direct converter. The output of the amplification unit is connected to a first direct input of the subtractor. An output of the subtractor is connected to the input of the analog-to-digital convertor. The modulator also includes a compensation filter located between the output of the subtractor and a second inverter input of the subtractor. When considering an impulse response of the modulator, at the output of the subtractor, to an impulse sent at the output of the subtractor, including a first part covering a first time interval 0; T with T≧&Dgr;t, and a second part covering a second time interval T; ∝, the compensation filter is designed to contribute to the first part and the amplification unit is designed to contribute only to the second part. Such a sigma-delta modulator may be used in a radar processing chain.

Abstract translation: 具有在模数转换器的输入端与数模转换器的输出之间的传播延迟DELTAt的Σ-Δ调制器。 减法器位于放大单元和模拟到直接转换器之间的直接链中。 放大单元的输出连接到减法器的第一直接输入。 减法器的输出连接到模数转换器的输入。 调制器还包括位于减法器的输出端和减法器的第二反相器输入端之间的补偿滤波器。 当考虑调制器的脉冲响应时，在减法器的输出处，到减法器的输出处发送的脉冲，包括覆盖第一时间间隔0的第一部分; T，其中T> = DELTAt，第二部分覆盖第二时间间隔T; 支路，补偿滤波器被设计成对第一部分有贡献，并且放大单元被设计成仅贡献于第二部分。 这样的Σ-Δ调制器可以用在雷达处理链中。

公开(公告)号：US07180974B2

公开(公告)日：2007-02-20

申请号：US11037460

申请日：2005-01-19

Applicant: Jean-Luc De Gouy ,  Pascal Gabet

Inventor： Jean-Luc De Gouy ,  Pascal Gabet

IPC: H03K21/00

CPC classification number: G06F7/68 ,  H03K23/68

Abstract: A method and device of frequency division with a division ratio: comprising: an input divider with a division ratio NPs receiving the frequency Fe at input and delivering a signal to an insertion/substitution divider, the insertion/substitution divider having an input of variation of the division ratio, delivering a command frame to the input divider and generating an end-of-count signal, the insertion/substitution divider being adapted to the insertion of one or more input divider cycles and/or the substitution of an input divider cycle in the command frame.

Abstract translation: 一种具有分频比的分频方法和装置，包括：输入分频器，分频比NPs在输入端接收频率Fe，并将信号传送到插入/取代分频器，插入/取代分频器具有 分配比率，将命令帧传递到输入分频器并产生计数结束信号，插入/替换分频器适于插入一个或多个输入分频器周期和/或替换输入分频器周期 命令帧。

公开(公告)号：US20050180539A1

公开(公告)日：2005-08-18

申请号：US11037460

申请日：2005-01-19

Applicant: Jean-Luc De Gouy ,  Pascal Gabet

Inventor： Jean-Luc De Gouy ,  Pascal Gabet

IPC: G06F7/68 ,  H03K23/50 ,  H03K23/66 ,  H03K23/68 ,  H03K21/00

CPC classification number: G06F7/68 ,  H03K23/68

Abstract: A method and device of frequency division with a division ratio: comprising: an input divider with a division ratio NPs receiving the frequency Fe at input and delivering a signal to an insertion/substitution divider, the insertion/substitution divider having an input of variation of the division ratio, delivering a command frame to the input divider and generating an end-of-count signal, the insertion/substitution divider being adapted to the insertion of one or more input divider cycles and/or the substitution of an input divider cycle in the command frame.

Abstract translation: 一种具有分频比的分频方法和装置，包括：输入分频器，分频比NPs在输入端接收频率Fe，并将信号传送到插入/取代分频器，插入/取代分频器具有 分配比率，将命令帧传递到输入分频器并产生计数结束信号，插入/替换分频器适于插入一个或多个输入分频器周期和/或替换输入分频器周期 命令帧。

公开(公告)号：US6075474A

公开(公告)日：2000-06-13

申请号：US105172

申请日：1998-06-26

Applicant: Pascal Gabet ,  Jean-Luc De Gouy

Inventor： Pascal Gabet ,  Jean-Luc De Gouy

IPC: H03M1/00 ,  G06F1/03 ,  H03M1/06 ,  H03M1/08 ,  H03M7/00 ,  H03M7/32 ,  H03M3/00 ,  H03M1/10

CPC classification number: G06F1/0328 ,  H03M7/3026 ,  H03M7/3037

Abstract: A device for the generation of analog signals by means of analog-digital converters comprises a block for the generation of words encoded on N bits and an analog-digital converter whose input is encoded on M bits, M being smaller than N. The device furthermore comprises a sigma-delta modulator, at the output of the first block, the bus being separated into M most significant bits reserved for the input of the analog-digital converter and N-M least significant bits that enter the sigma-delta modulator, the output of this modulator being an M-bit bus that is added to the M output bits of the word generation block by digital addition means, M being smaller than N.

Abstract translation: 用于通过模数转换器产生模拟信号的装置包括用于产生以N位编码的字的块和模拟数字转换器，其输入以M位编码，M小于N.此外，该装置 包括Σ-Δ调制器，在第一块的输出处，总线被分离为M模拟数字转换器的输入保留的最高有效位和进入Σ-Δ调制器的NM最低有效位，输出 该调制器是通过数字加法装置加到字生成块的M个输出位的M比特总线，M小于N.

公开(公告)号：US20050179475A1

公开(公告)日：2005-08-18

申请号：US11038487

申请日：2005-01-21

Applicant: Jean-Luc De Gouy ,  Pascal Gabet

Inventor： Jean-Luc De Gouy ,  Pascal Gabet

IPC: H03K23/40 ,  H03K23/54 ,  H03K23/66 ,  H03K21/00

CPC classification number: H03K23/544 ,  H03K23/665

Abstract: A divider to divide a frequency Fe comprises at least the following elements: three flip-flop circuits, each of the flip-flop circuits receiving the frequency to be divided, every feedback loop between an output of a flip-flop circuit and its input or the input of the other flip-flop circuits comprising a single multiplexer, wherein one of the flip-flop circuits commands the loading of all the flip-flop circuits during one period of the frequency A multiplexer has two inputs, one selection bit and one output and is integrated into a flip-flop circuit.

Abstract translation: 至少分成以下元件的分频器：三个触发器电路，每个触发器电路接收要被分频的频率，每个反馈回路在 触发器电路及其输入或包括单个多路复用器的其它触发器电路的输入，其中触发器电路中的一个命令在频率A多路复用器具有两个触发器电路的一个周期期间所有触发器电路的加载 输入，一个选择位和一个输出，并被集成到触发器电路中。

公开(公告)号：US06559712B2

公开(公告)日：2003-05-06

申请号：US10042199

申请日：2002-01-11

Applicant: Pascal Gabet ,  Jean-Luc De Gouy

Inventor： Pascal Gabet ,  Jean-Luc De Gouy

IPC: H03B100

CPC classification number: G06J1/00

Abstract: A method and device for the generation of a random signal, comprising: A first step (a) for the generation of a pseudo-random signal, a second step (b) for the filtering (F1) of the signal coming from the step (a) to obtain a signal x(t) having a predetermined spectral envelope H(f), a third step (c) in which a non-linear function g is applied to the signal x(t) so as to form a signal y(t) and create overshoots on the edges of the histogram of the signal y(t), a fourth filtering (F2) step (d) used to smoothen the overshoots of the histogram of the signal y(t), compensate for the effect of the non-linearity and carry out an additional filtering at (F1). Application to a system of analog-digital conversion or digital-analog conversion.

Abstract translation: 一种用于产生随机信号的方法和装置，包括：用于产生伪随机信号的第一步骤（a），用于对来自步骤的信号进行滤波（F1）的第二步骤（b） a）获得具有预定频谱包络H（f）的信号x（t），其中将非线性函数g施加到信号x（t）的第三步骤（c），以形成信号y （t）并在信号y（t）的直方图的边缘上产生过冲，用于平滑信号y（t）的直方图的过冲的第四滤波（F2）步骤（d），补偿效应 的非线性，并在（F1）处进行附加滤波。应用于模拟数字转换或数模转换系统。