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公开(公告)号：US5619729A
公开(公告)日：1997-04-08
申请号：US584805
申请日：1996-01-11
申请人： Patrick M. Bland , Richard G. Hofmann , Robert T. Jackson , Nader Amini , Bechara F. Boury , Jayesh Joshi
发明人： Patrick M. Bland , Richard G. Hofmann , Robert T. Jackson , Nader Amini , Bechara F. Boury , Jayesh Joshi
CPC分类号： G06F1/3225 , G06F1/3275 , G06F13/28 , Y02B60/1225 , Y02B60/1228
摘要： A device and method for power management of direct memory access ("DMA") slaves through DMA traps. The device comprises a plurality of registers coupled with conventional logic in order to generate a control signal for disabling direct memory access transfer requests for a powered-off DMA slave until the slave is re-powered. The method for managing power comprises steps of unmasking bits in a register containing information regarding which DMA slaves have been powered-off. Next, the DMA Controller consults a power management macro ("PMM") to determine whether a DMA transfer request involves a powered-off DMA slave. If not, the DMA transfer continues. However, if the DMA transfer does involve a powered-off DMA slave, then a main software application in operation is temporarily halted and the PMM generates a SMI signal and outputs the SMI signal to the central processing unit ("CPU") while keeping the disable control signal asserted, which effectively disables the DMA channel. The SMI signal invokes a software service routine which re-powers the powered-off DMA slave so that the main software application can continue.
摘要翻译： 通过DMA陷阱对直接存储器访问（“DMA”）从站进行电源管理的设备和方法。 该装置包括与常规逻辑耦合的多个寄存器，以便产生一个控制信号，用于禁用关闭DMA从器件的直接存储器访问传输请求，直到从器件被重新供电为止。 用于管理功率的方法包括以下步骤：在包含关于哪个DMA从设备已断电的信息的寄存器中取消屏蔽位。 接下来，DMA控制器查询电源管理宏（“PMM”）以确定DMA传输请求是否涉及关闭的DMA从机。 否则，DMA传输继续。 然而，如果DMA传输确实涉及关闭的DMA从器件，则暂时停止正在运行的主要软件应用程序，并且PMM生成SMI信号并将SMI信号输出到中央处理器（“CPU”），同时保持 禁用控制信号有效，从而有效地禁用DMA通道。 SMI信号调用一个软件服务程序，重新供电关闭的DMA从站，使主软件应用程序能够继续运行。
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公开(公告)号：US5546568A
公开(公告)日：1996-08-13
申请号：US176944
申请日：1993-12-29
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , Y02B60/1217 , Y02B60/32
摘要： The present invention relates to an apparatus and method for controlling a CPU clock in response to certain events with a system in order to conserve power usage. These events can be programmably enabled or disabled. The apparatus comprises a circuit for detecting enabled Stop Clock events requiring the CPU clock to temporarily cease operation. In combination therewith, the present invention includes a circuit for detecting enabled Stop Break events which are used to re-start the CPU clock. The present invention further comprises a Speedup circuitry to increase the CPU clock speed for enabled speedup events which are dependent on CPU clock speed.
摘要翻译： 本发明涉及一种用于响应于系统的某些事件来控制CPU时钟以便节省功率使用的装置和方法。 这些事件可以可编程地启用或禁用。 该装置包括用于检测启用的停止时钟事件的电路，其要求CPU时钟暂时停止操作。 与此相结合，本发明包括用于检测用于重新启动CPU时钟的启用停止事件的电路。 本发明还包括加速电路，以增加取决于CPU时钟速度的启用加速事件的CPU时钟速度。
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公开(公告)号：US5630147A
公开(公告)日：1997-05-13
申请号：US601697
申请日：1996-02-15
申请人： Sham Datta , Jayesh Joshi , James P. Kardach
发明人： Sham Datta , Jayesh Joshi , James P. Kardach
CPC分类号： G06F1/3253 , G06F1/3203 , Y02B60/1235
摘要： A device and method for transferring data, address and status information concerning a former I/O bus cycle before a system management interrupt is initiated. A plurality of system management shadow registers samples information from a system bus. Such information is obtained by a register accessing the plurality of system management shadow registers through a common shadow port.
摘要翻译： 一种用于在系统管理中断启动之前传送有关前一个I / O总线周期的数据，地址和状态信息的设备和方法。 多个系统管理影子寄存器从系统总线采样信息。 这样的信息通过通过公共影子端口访问多个系统管理影子寄存器的寄存器获得。
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