利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

74 条记录 (耗时 0.035 秒)

    Access nodes for giving a client device access to an internet network
    1.
    发明申请
    Access nodes for giving a client device access to an internet network 审中-公开
    用于给客户端设备访问互联网的接入节点

    公开(公告)号：US20070220011A1

    公开(公告)日：2007-09-20

    申请号：US11524282

    申请日：2006-09-21

    申请人： Paul Cautereels ,  Michael Beck ,  Tim Vermeiren ,  Hans Maurice Felix Dequeker ,  Tim Gyselings

    发明人： Paul Cautereels ,  Michael Beck ,  Tim Vermeiren ,  Hans Maurice Felix Dequeker ,  Tim Gyselings

    IPC分类号： G06F17/30

    CPC分类号： H04L12/2885 ,  H04L12/2896 ,  H04L41/0893 ,  H04L67/02 ,  H04L67/28 ,  H04L67/30 ,  H04L69/329

    摘要： Access nodes (1) for giving client devices (2,3) access to internet networks (5) comprise detectors (11) for detecting request messages in client information defining requests for receiving media contents and are provided with processors (12) for processing detections of the request messages for gathering statistical information about the media contents. The statistical information comprises viewing figures per media content. Further request messages in the client information define further requests for finishing receptions of the media contents for gathering further statistical information. The further statistical information comprises timing figures per media content. Data messages define client data with respect to the media contents for gathering yet further statistical information. The yet further statistical information comprises appreciation figures and/or yet further viewing figures per media content. The access nodes (1) are further provided with couplers (14) and controllers (13) for controlling the couplers (14) for supplying a same media content to several client devices (2,3) simultaneously. The client information comprises internet group management protocol messages such as join messages and leave messages.

    摘要翻译： 用于给客户端设备（2,3）访问互联网（5）的接入节点（1）包括检测器（11），用于检测定义用于接收媒体内容的请求的客户端信息中的请求消息，并提供处理器（12），用于处理检测 用于收集关于媒体内容的统计信息的请求消息。 统计信息包括查看每个媒体内容的数据。 在客户端信息中的进一步的请求消息定义了用于收集进一步统计信息的媒体内容的接收的进一步请求。 进一步的统计信息包括每个媒体内容的定时图。 数据消息定义关于媒体内容的客户端数据，以收集更多的统计信息。 进一步的统计信息包括每个媒体内容的欣赏数字和/或进一步查看数据。 接入节点（1）还具有耦合器（14）和控制器（13），用于控制用于同时向多个客户机设备（2,3）提供相同媒体内容的耦合器（14）。 客户端信息包括互联网组管理协议消息，例如加入消息和离开消息。

    METHOD TO PRESERVE THE ORDER OF PACKETS OF A SAME FLOW AND TRANSMITTED EITHER THROUGH A CONTROL PLANE OR THROUGH A DATA PLANE OF A TELECOMMUNICATION NETWORK ELEMENT
    2.
    发明申请
    METHOD TO PRESERVE THE ORDER OF PACKETS OF A SAME FLOW AND TRANSMITTED EITHER THROUGH A CONTROL PLANE OR THROUGH A DATA PLANE OF A TELECOMMUNICATION NETWORK ELEMENT 审中-公开
    通过控制平面或通过电信网络元件的数据平面来保存同一流程的分组和传输的分组的方法

    公开(公告)号：US20070140124A1

    公开(公告)日：2007-06-21

    申请号：US11567699

    申请日：2006-12-06

    申请人： Steven BOUCQUE ,  Michael Beck ,  Eric Borghs ,  Paul Cautereels ,  Patrick Renaux

    发明人： Steven BOUCQUE ,  Michael Beck ,  Eric Borghs ,  Paul Cautereels ,  Patrick Renaux

    IPC分类号： H04J1/16 ,  H04L12/56

    CPC分类号： H04L47/10 ,  H04L47/34

    摘要： A method to preserve the ordering of data packets of a same flow (P1-P4, P7, P8) passing either through a control plane (CP) or through a data plane (DP) of a telecommunication network element. The method comprises the step of, when the control plane starts processing the new flow, the control plane controls the data plane to latch any other packet belonging to this flow by sending a first control packet (C1) to said data plane. When the processing is completed, the control plane controls the data plane to release the latched packets by sending a second control packet (C3) to said data plane. The present method is particularly applicable to Ethernet frames, where it is also not allowed to reorder frames belonging to a same ‘Ethernet flow’.

    摘要翻译： 一种保持通过控制平面（CP）或通过电信网络元件的数据平面（DP）的相同流（P 1 -P 4，P 7，P 8）的数据分组排序的方法。 该方法包括以下步骤：当控制平面开始处理新流时，控制平面通过向第一数据平面发送第一控制分组（C 1）来控制数据平面以锁存属于该流的任何其他分组。 当处理完成时，控制平面通过向所述数据平面发送第二控制分组（C 3）来控制数据平面以释放锁存的分组。 本方法特别适用于以太网帧，其中也不允许对属于相同“以太网流”的帧进行重新排序。

    DECENTRALIZED INFORMATION SHARING NETWORK
    3.
    发明申请
    DECENTRALIZED INFORMATION SHARING NETWORK 审中-公开

    公开(公告)号：US20190173854A1

    公开(公告)日：2019-06-06

    申请号：US16198296

    申请日：2018-11-21

    申请人： Michael Beck

    发明人： Michael Beck

    IPC分类号： H04L29/06 ,  H04L9/32 ,  H04L9/06 ,  H04L29/08

    摘要： A payload data can be received. The payload data can be packaged into a first immutable secure container at a first secure system. A new block of a blockchain can be created. The new block of the block chain can be separate from the first secure system. The new block can include a proof of existence of the payload data.

    Crack stops for semiconductor devices
    4.
    发明授权
    Crack stops for semiconductor devices 有权
    半导体器件的裂纹停止

    公开(公告)号：US08309435B2

    公开(公告)日：2012-11-13

    申请号：US13160214

    申请日：2011-06-14

    申请人： Erdem Kaltalioglu ,  Michael Beck

    发明人： Erdem Kaltalioglu ,  Michael Beck

    IPC分类号： H01L23/544

    CPC分类号： H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

    摘要翻译： 公开了用于半导体器件，半导体器件和制造半导体器件的方法的裂纹停止。 在一个实施例中，用于半导体器件的阻挡结构包括多个基本上V形的区域。 多个基本V形区域中的每一个被设置成与多个基本V形区域中的另一个相邻。

    Crack stops for semiconductor devices
    6.
    发明授权
    Crack stops for semiconductor devices 有权
    半导体器件的裂纹停止

    公开(公告)号：US08008750B2

    公开(公告)日：2011-08-30

    申请号：US12024758

    申请日：2008-02-01

    申请人： Erdem Kaltalioglu ,  Michael Beck

    发明人： Erdem Kaltalioglu ,  Michael Beck

    IPC分类号： H01L23/544

    CPC分类号： H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

    摘要翻译： 公开了用于半导体器件，半导体器件和制造半导体器件的方法的裂纹停止。 在一个实施例中，用于半导体器件的阻挡结构包括多个基本上V形的区域。 多个基本V形区域中的每一个被设置成与多个基本V形区域中的另一个相邻。

    System, method and operating unit for forming mixed layers for pallets
    7.
    发明申请
    System, method and operating unit for forming mixed layers for pallets 有权
    用于形成托盘混合层的系统，方法和操作单元

    公开(公告)号：US20100228385A1

    公开(公告)日：2010-09-09

    申请号：US12660727

    申请日：2010-03-03

    申请人： Michael Beck ,  Markus Ludsteck

    发明人： Michael Beck ,  Markus Ludsteck

    IPC分类号： G06F7/00 ,  B65G57/00 ,  G06F3/048

    CPC分类号： B65G1/1378 ,  B65G47/086 ,  B65G57/24 ,  B65G60/00 ,  B65G61/00

    摘要： A system (1), a method and an operating unit (62) for the creation of mixed layers for pallets (81, 82, 83, 84) are disclosed. A storage (10) is provided in which at least two different pack types are stored on a plurality of pallets (81, 82, 83, 84), including a plurality of layers of homogenous packs. The packs are intermediately stored in a plurality of individual, parallel conveyors (301, 302, . . . 30N) in a homogenous state. Based on the input of a user (5) on a touch panel (62), the packs are supplied to a grouping table (50) via a supply conveyor (40) in a predetermined sequence. A controller (60) is associated with the system (1) so that, in the grouping table (50), individual different pack types are allocated to the predefined positions of the different pack types as a function of predefined positions of the different pack types in a layer pattern (14) of a layer (24) of a production pallet (12).

    摘要翻译： 公开了一种用于产生用于托盘（81,82,83,84）的混合层的方法和操作单元（62）。 提供了一种存储装置，其中至少两种不同的包装类型存储在多个包括多层均匀包装的托盘（81,82,83,84）中。 这些包装以均匀的状态中间存储在多个单独的平行输送机（301,302，...，30N）中。 基于触摸面板（62）上的用户（5）的输入，经由供给传送器（40）以预定的顺序将包提供给分组表（50）。 控制器（60）与系统（1）相关联，使得在分组表（50）中，根据不同包装类型的预定位置的函数将单独的不同包类型分配给不同包类型的预定义位置 在生产托盘（12）的层（24）的层图案（14）中。

    Method and Apparatus for Reducing Charge Trapping in High-K Dielectric Material
    8.
    发明申请
    Method and Apparatus for Reducing Charge Trapping in High-K Dielectric Material 有权
    用于降低高K电介质材料电荷捕获的方法和装置

    公开(公告)号：US20100054022A1

    公开(公告)日：2010-03-04

    申请号：US12201223

    申请日：2008-08-29

    申请人： Michael Beck ,  Martin Kerber ,  Peter Lahnor ,  Roland Thewes

    发明人： Michael Beck ,  Martin Kerber ,  Peter Lahnor ,  Roland Thewes

    IPC分类号： G11C11/24 ,  G11C7/00

    CPC分类号： G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4068

    摘要： In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

    摘要翻译： 在一个实施例中，集成电路包括具有多个电容器的存储器阵列，用于在初始状态下存储存储器阵列中初始状态的数据。 集成电路还包括用于偶尔反转由多个电容器存储的数据的电路，并且跟踪由多个电容器存储的数据的当前状态是否对应于初始状态。 当数据的当前状态不对应于初始状态时，电路在读取操作期间将从存储器阵列读出的数据反相。

    Metal interconnect structure and method
    9.
    发明授权
    Metal interconnect structure and method 有权
    金属互连结构和方法

    公开(公告)号：US07651942B2

    公开(公告)日：2010-01-26

    申请号：US11203883

    申请日：2005-08-15

    申请人： Frank Huebinger ,  Michael Beck

    发明人： Frank Huebinger ,  Michael Beck

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814

    摘要： A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.

    摘要翻译： 一种制造半导体器件的方法，该半导体器件包括具有形成在第一介电层中的导电区域的金属互连结构和上覆的低k电介质层。 在上覆电介质层中的双镶嵌结构中形成通孔和沟槽，通孔与导电区域和沟槽对准。 用于释放有机残余物的牺牲衬垫沉积在晶片的通孔和上表面上，沉积有机平坦化层。 用干等离子体蚀刻除去有机平坦化层，然后进行湿法清洁以除去牺牲衬垫。 将导电材料与电介质层分离的扩散阻挡层沉积在双镶嵌结构上并在晶片的上表面上。 导电结构形成在扩散阻挡层上并被抛光以形成用于进一步处理步骤的均匀表面。

    Integrated circuit manufacturing method using hard mask
    10.
    发明授权
    Integrated circuit manufacturing method using hard mask 有权
    使用硬掩模的集成电路制造方法

    公开(公告)号：US07615484B2

    公开(公告)日：2009-11-10

    申请号：US11739595

    申请日：2007-04-24

    申请人： Wuping Liu ,  Michael Beck ,  John A. Fitzsimmons

    发明人： Wuping Liu ,  Michael Beck ,  John A. Fitzsimmons

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76804 ,  H01L21/02063 ,  H01L21/76814 ,  H01L21/76835

    摘要： An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

    摘要翻译： 提供一种集成电路硬掩模处理系统，包括提供具有集成电路的基板; 在所述集成电路上形成互连层; 在所述互连层上施加低K电介质层; 在低K电介质层上施加硬掩模层; 通过所述硬掩模层和所述低K电介质层形成通孔至所述互连层; 在所述通孔开口中施加第一流体和第二流体以去除所述硬掩模层的突出端; 在所述通孔开口中沉积互连金属; 并对互连金属和超低K电介质层进行化学机械抛光。