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1.发明授权公开(公告)号：US07433912B1
公开(公告)日：2008-10-07
申请号：US10782162
申请日：2004-02-19
IPC分类号： G06F7/533
CPC分类号： G06F7/5324 , G06F2207/3812 , G06F2207/382 , G06F2207/3824
摘要： A unified data flow is provided that allows multiplication of SIMD and non-SIMD multiplies in one multiplier. The multiplies may be both integer and floating point operations. The multiplier is partitionable having a plurality of sub-trees. The multiplier is configured to be a single tree structure in response to a non-SIMD multiplication instruction and as a partitioned tree structure in response to a SIMD multiplication instruction. At least two multiplication operations can be performed in parallel in the partitioned tree structure in response to the SIMD multiplication instruction and a single multiplication operation is performed in the single tree structure in response to the non-SIMD multiplication instruction. Appropriate formatting of the input operands and selection of data from the tree structures is performed in accordance with the instruction.
摘要翻译： 提供统一的数据流，允许SIMD和非SIMD乘法在一个乘法器中相乘。 乘法可以是整数和浮点运算。 乘法器是可分割的，具有多个子树。 乘法器被配置为响应于非SIMD乘法指令而是单个树结构，并且响应于SIMD乘法指令而被配置为分区树结构。 可以响应于SIMD乘法指令在分区树结构中并行执行至少两个乘法运算，并且响应于非SIMD乘法指令在单个树结构中执行单个乘法运算。 根据该指令执行输入操作数的适当格式化和从树结构中选择数据。
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2.发明授权Partitioned shifter for single instruction stream multiple data stream (SIMD) operations 有权用于单指令流分多个数据流（SIMD）操作的分区移位器公开(公告)号：US07099910B2
公开(公告)日：2006-08-29
申请号：US10408132
申请日：2003-04-07
IPC分类号： G06F7/485
CPC分类号： G06F7/485 , G06F5/012 , G06F2207/382 , G06F2207/3828
摘要： A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normalizer, selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed, and selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
摘要翻译： 一种在单个浮点执行单元内实现单指令流多数据流操作和双精度浮点运算的方法，该方法包括：提供具有双向对准器和双向归一化器的浮点单元， 要执行单个指令流多数据流操作还是执行双精度操作，并且基于是要执行单个指令流多数据流操作还是双精度操作来选择性地归一化值 被执行。
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3.发明授权Low latency integer divider and integration with floating point divider and method 有权低延迟整数分频器，并与浮点分频器和方法集成公开(公告)号：US07539720B2
公开(公告)日：2009-05-26
申请号：US11014026
申请日：2004-12-15
CPC分类号： G06F7/4873 , G06F7/5375
摘要： A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normalizes the dividend and divisor, and calculates NDQ number of quotient digits from the normalized divisor and dividend.
摘要翻译： 一种方法和设备将除数除以除数，除数和除数均为整数。 该方法和装置根据除数和有效数字的有效数字的数量确定最大可能数量的商数（NDQ），对股息和除数进行归一化，并从归一化除数和股息计算商数的NDQ数。
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4.发明申请SINGLE CYCLE DATA MOVEMENT BETWEEN GENERAL PURPOSE AND FLOATING-POINT REGISTERS 有权一般用途和浮点注册机之间的单循环数据移动公开(公告)号：US20100306510A1
公开(公告)日：2010-12-02
申请号：US12476636
申请日：2009-06-02
CPC分类号： G06F9/30032 , G06F9/30014 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/3885
摘要： Systems and methods for providing single cycle movement of data between a floating-point register file (FRF) and a general purpose or integer register file (RF) of a microprocessor system are provided. The system may include an integer execution unit operative to execute instructions with single cycle latency, a floating-point execution unit, a working register file (WRF), an FRF, and an IRF. To achieve the single cycle movement functionality, the integer execution unit may physically own the WRF, IRF, and FRF, and may monitor and control any dependencies between them. Thus, since the integer execution unit has direct read access to both the IRF and the FRF, data may be moved between the two register files using the single cycle operation of the integer execution unit, without the need to store and load the data from memory.
摘要翻译： 提供了一种用于在微处理器系统的浮点寄存器文件（FRF）和通用或整数寄存器文件（RF）之间提供单周期数据移动的系统和方法。 系统可以包括可执行具有单周期延迟的指令的整数执行单元，浮点执行单元，工作寄存器文件（WRF），FRF和IRF。 为了实现单循环移动功能，整数执行单元可以物理拥有WRF，IRF和FRF，并且可以监视和控制它们之间的任何依赖关系。 因此，由于整数执行单元具有对IRF和FRF两者的直接读取访问，所以可以使用整数执行单元的单周期操作在两个寄存器文件之间移动数据，而不需要从存储器存储和加载数据 。
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5.发明授权Single cycle data movement between general purpose and floating-point registers 有权通用和浮点寄存器之间的单周期数据移动公开(公告)号：US09304767B2
公开(公告)日：2016-04-05
申请号：US12476636
申请日：2009-06-02
CPC分类号： G06F9/30032 , G06F9/30014 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/3885
摘要： Systems and methods for providing single cycle movement of data between a floating-point register file (FRF) and a general purpose or integer register file (IRF) of a microprocessor system are provided. The system may include an integer execution unit operative to execute instructions with single cycle latency, a floating-point execution unit, a working register file (WRF), an FRF, and an IRF. To achieve the single cycle movement functionality, the integer execution unit may physically own the WRF, IRF, and FRF, and may monitor and control any dependencies between them. Thus, since the integer execution unit has direct read access to both the IRF and the FRF, data may be moved between the two register files using the single cycle operation of the integer execution unit, without the need to store and load the data from memory.
摘要翻译： 提供了一种用于在微处理器系统的浮点寄存器堆（FRF）和通用或整数寄存器文件（IRF）之间提供单周期数据移动的系统和方法。 系统可以包括可执行具有单周期延迟的指令的整数执行单元，浮点执行单元，工作寄存器文件（WRF），FRF和IRF。 为了实现单循环移动功能，整数执行单元可以物理拥有WRF，IRF和FRF，并且可以监视和控制它们之间的任何依赖关系。 因此，由于整数执行单元具有对IRF和FRF两者的直接读取访问，所以可以使用整数执行单元的单周期操作在两个寄存器文件之间移动数据，而不需要从存储器存储和加载数据 。
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6.发明授权Processor which implements fused and unfused multiply-add instructions in a pipelined manner 有权处理器，以流水线方式实现融合和未分配的加法指令公开(公告)号：US08239440B2
公开(公告)日：2012-08-07
申请号：US12057894
申请日：2008-03-28
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443 , G06F2207/3884
摘要： Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.
摘要翻译： 在融合的乘法加法管道中实现未经加密的乘法加法指令。 系统可以包括具有用于接收加法项的输入的对准器，具有用于接收第一值的两个输入和用于乘法的第二值的乘法器树，以及第一进位保存加法器（CSA），其中第一CSA可以接收部分 乘数树中的乘积和对准器的对齐加法项。 该系统可以包括可以接收第一部分乘积，第二部分乘积和对齐的加法项的融合/未融合乘法（FUMA）块，其中第一部分乘积和第二部分乘积不被截断。 FUMA块可以使用第一部分乘积，第二部分积和对齐的相加项来执行未融合的加法运算或融合乘法运算，例如取决于操作码或模式位。
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公开(公告)号：US20110089307A1
公开(公告)日：2011-04-21
申请号：US12432938
申请日：2009-04-30
CPC分类号： A47G1/0616 , A46B15/0085 , A46B15/0095 , A46B15/0097 , A46B2200/1066 , B26B21/52 , B43K23/001 , B43K23/02 , B43K23/12 , B43K23/126 , B43K25/022 , B43K25/024 , B43K25/026 , B43K25/028 , B43K29/00 , B43K29/007
摘要： The present invention is directed to a support for hand-held instruments providing for display of an image sheet in both a deployed or in use position and a raised or stored position. The present invention is available for use across a variety of applications that utilize hand-held instrument where an image display is desired. Uses include but are not limited to hand-held device such as writing instruments, toothbrushes, razors, and the like. The present invention provides for a leg assembly positioned near one end of the hand-held instrument, wherein the leg assembly can extend or pivot from the stored position to a use position for the purpose of holding and stabilizing the instrument on a horizontal surface and positioning the instrument in an angled-upward direction to allow for ease of grasp by a user while simultaneously displaying an image within an image holder of the leg assembly.
摘要翻译： 本发明涉及一种用于在展开或使用位置以及升高或储存位置中显示图像片的手持式仪器的支撑件。 本发明可用于使用需要图像显示的手持式仪器的各种应用。 用途包括但不限于书写工具，牙刷，剃须刀等手持装置。 本发明提供一种腿部组件，其位于手持式工具的一端附近，其中腿部组件可以从存储位置延伸或枢转到使用位置，以便将仪器保持并稳定在水平表面上并定位 仪器处于向上倾斜的方向，以允许使用者容易掌握，同时在腿部组件的图像保持器内显示图像。
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8.发明申请MECHANISM FOR HANDLING UNFUSED MULTIPLY-ACCUMULATE ACCRUED EXCEPTION BITS IN A PROCESSOR 有权在处理器中处理未充分的多余累加的例外的机制公开(公告)号：US20100268920A1
公开(公告)日：2010-10-21
申请号：US12424929
申请日：2009-04-16
IPC分类号： G06F9/302
CPC分类号： G06F11/0772 , G06F9/3001 , G06F9/30014 , G06F9/30094 , G06F9/30101 , G06F9/3017 , G06F9/3851 , G06F9/3853 , G06F9/3865 , G06F9/3889
摘要： A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.
摘要翻译： 用于处理未被使用的加法累加异常位的机制包括包括浮点单元，存储和异常逻辑的处理器。 浮点单元可以被配置为执行用指令集体系结构（ISA）定义的未融合的乘法累加指令。 未发送的乘法累加指令可以包括乘法子操作和累加子操作。 存储器可以被配置为保持浮点异常状态信息。 异常逻辑可以被配置为例如在乘法子操作完成之后并且在累加子操作完成之前捕获浮点异常状态，并且更新存储以反映浮点异常状态。
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公开(公告)号：US20100222728A1
公开(公告)日：2010-09-02
申请号：US12680922
申请日：2008-10-03
申请人： Jeffrey S. Brooks
发明人： Jeffrey S. Brooks
IPC分类号： A61F5/01
CPC分类号： A61F13/068
摘要： A body pad for application to the skin for treating an ailment. The pad includes a pad body, a recess in the pad body extending from the outer surface of the pad body toward the inner surface a distance which is less than an overall thickness of the body, and a thin, flexible wall at a bottom of the recess. The wall is adapted to deform outwardly into the recess to provide a cavity between the pad body and the skin for holding a volume of medication which has been pre-applied to the skin. Other pad features are disclosed.
摘要翻译： 用于皮肤治疗疾病的身体垫。 衬垫包括衬垫本体，衬垫本体中的凹部，从衬垫本体的外表面向内表面延伸的距离小于主体的整体厚度;以及位于底部的薄的柔性壁 休息。 所述壁适于向外变形到所述凹部中，以在所述垫体和皮肤之间提供空腔，用于保持预先施加到皮肤上的一定量的药物。 公开了其他垫特征。
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10.发明授权公开(公告)号：US07373489B1
公开(公告)日：2008-05-13
申请号：US10880713
申请日：2004-06-30
CPC分类号： G06F9/3851 , G06F9/30014 , G06F9/3828 , G06F9/3861 , G06F9/3867
摘要： An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.
摘要翻译： 一种用于浮点异常预测和恢复的装置和方法。 在一个实施例中，处理器可以包括指令提取逻辑，其被配置为从多个线程中的一个发出第一指令，并且从多个线程中的另一个线程连续地发出第二指令。 处理器还可以包括浮点算术逻辑，其被配置为执行由指令提取逻辑从多个线程中的给定一个发出的浮点指令，并且还被配置为确定浮点指令是否生成异常，以及 还可以包括被配置为预测浮点指令是否将产生异常的异常预测逻辑，其中在浮点运算逻辑确定浮点指令是否产生异常之前发生预测。
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