公开(公告)号：US08250339B2

公开(公告)日：2012-08-21

申请号：US11962979

申请日：2007-12-21

申请人： Paul L. Master ,  Stephen J. Smith ,  John Watson

发明人： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC分类号： G06F13/00

CPC分类号： G06F15/80 ,  G06F7/57 ,  G06F9/44505 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

摘要翻译： 本发明涉及用于自适应计算的新类别的集成电路的配置。 各种实施例提供用于自适应计算引擎（ACE）集成电路的可执行信息模块，并且可以包括配置信息，操作数数据，并且还可以包括路由和功率控制信息。 ACE IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络用于为多个不同的功能模式配置多个异构计算元件。

公开(公告)号：US20090172137A1

公开(公告)日：2009-07-02

申请号：US12399671

申请日：2009-03-06

申请人： Paul L. Master ,  Stephen J. Smith ,  John Watson

发明人： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC分类号： G06F15/177

CPC分类号： G06F15/7867 ,  G06F13/40 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.

摘要翻译： 本发明涉及用于自适应或可重新配置计算的新类别的集成电路的配置。 优选的自适应计算引擎（ACE）IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，控制器操作，存储器操作 和位级操作。 优选的系统实施例包括耦合到提供操作模式所需的配置信息的ACE集成电路。 优选的方法包括生成和提供各种操作模式的配置信息的各种手段。

公开(公告)号：US06986021B2

公开(公告)日：2006-01-10

申请号：US09997987

申请日：2001-11-30

申请人： Paul L. Master ,  Stephen J. Smith ,  John Watson

发明人： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC分类号： G06F13/00

CPC分类号： G06F15/80 ,  G06F7/57 ,  G06F9/44505 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit to provide an operating mode. The preferred executable information modules include configuration information interleaved with operand data, and may also include routing and power control information. The preferred ACE IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

公开(公告)号：US20120317397A1

公开(公告)日：2012-12-13

申请号：US13589583

申请日：2012-08-20

申请人： Paul L. Master ,  Stephen J. Smith ,  John Watson

发明人： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC分类号： G06F15/76

CPC分类号： G06F15/80 ,  G06F7/57 ,  G06F9/44505 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

摘要翻译： 本发明涉及用于自适应计算的新类别的集成电路的配置。 各种实施例提供用于自适应计算引擎（ACE）集成电路的可执行信息模块，并且可以包括配置信息，操作数数据，并且还可以包括路由和功率控制信息。 ACE IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络用于为多个不同的功能模式配置多个异构计算元件。

公开(公告)号：US08412915B2

公开(公告)日：2013-04-02

申请号：US09997530

申请日：2001-11-30

申请人： Paul L. Master ,  Stephen J. Smith ,  John Watson

发明人： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC分类号： G06F15/00

CPC分类号： G06F15/7867 ,  G06F13/40 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.

公开(公告)号：US07320062B2

公开(公告)日：2008-01-15

申请号：US11241009

申请日：2005-09-30

申请人： Paul L. Master ,  Stephen J. Smith ,  John Watson

发明人： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC分类号： G06F13/00

CPC分类号： G06F15/80 ,  G06F7/57 ,  G06F9/44505 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

摘要翻译： 本发明涉及用于自适应计算的新类别的集成电路的配置。 各种实施例提供用于自适应计算引擎（ACE）集成电路的可执行信息模块，并且可以包括配置信息，操作数数据，并且还可以包括路由和功率控制信息。 ACE IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络用于为多个不同的功能模式配置多个异构计算元件。

公开(公告)号：US08880849B2

公开(公告)日：2014-11-04

申请号：US13589583

申请日：2012-08-20

申请人： Paul L. Master ,  Stephen J. Smith ,  John Watson

发明人： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC分类号： G06F13/00 ,  G06F15/78

CPC分类号： G06F15/80 ,  G06F7/57 ,  G06F9/44505 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

摘要翻译： 本发明涉及用于自适应计算的新类别的集成电路的配置。 各种实施例提供用于自适应计算引擎（ACE）集成电路的可执行信息模块，并且可以包括配置信息，操作数数据，并且还可以包括路由和功率控制信息。 ACE IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络用于为多个不同的功能模式配置多个异构计算元件。

公开(公告)号：US08225073B2

公开(公告)日：2012-07-17

申请号：US12399671

申请日：2009-03-06

申请人： Paul L. Master ,  Stephen J. Smith ,  John Watson

发明人： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F15/7867 ,  G06F13/40 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.

摘要翻译： 本发明涉及用于自适应或可重新配置计算的新类别的集成电路的配置。 优选的自适应计算引擎（ACE）IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，控制器操作，存储器操作 和位级操作。 优选的系统实施例包括耦合到提供操作模式所需的配置信息的ACE集成电路。 优选的方法包括生成和提供各种操作模式的配置信息的各种手段。

公开(公告)号：US20090325555A1

公开(公告)日：2009-12-31

申请号：US12554402

申请日：2009-09-04

申请人： Paul L. Master ,  John Watson

发明人： Paul L. Master ,  John Watson

IPC分类号： H04M3/42 ,  G06Q30/00 ,  G06Q50/00

CPC分类号： G06Q30/02

摘要： A system for efficient sale of devices that comply with licensed standards. A preferred embodiment of the invention uses a generic, or highly adaptable, hardware device. The device can be adapted to adhere to a specific standard, e.g., code-division multiple access, time-division multiple access, etc., after manufacture such as at the point-of-sale to an end user, prior to distribution, or at some other point in a distribution and sales network. This allows manufacturers, retailers and end users to benefit from more competitive selection of standardized communication, data and other formats. Reduction of manufacturing costs and elimination of shipping, or other transfer and storage costs, is also realized.

摘要翻译： 一种高效销售符合许可标准的设备的系统。 本发明的优选实施例使用通用或高适应性的硬件设备。 该设备可以在分发之前适应于遵守特定标准，例如在制造之后的码分多址，时分多路访问等，在销售点到最终用户，或者 在分销和销售网络的其他一点。 这允许制造商，零售商和最终用户从更具竞争力的标准化通信，数据和其他格式的选择中受益。 降低制造成本和消除运输，或其他转运和储存成本也得以实现。

公开(公告)号：US07961226B2

公开(公告)日：2011-06-14

申请号：US12560018

申请日：2009-09-15

申请人： Paul L. Master ,  John Watson

发明人： Paul L. Master ,  John Watson

IPC分类号： H04N5/228

CPC分类号： G06F7/5443 ,  G06F7/4806 ,  G06F9/3001 ,  G06F9/3885 ,  G06F9/3897 ,  H03H17/0294

摘要： The present invention provides a digital imaging apparatus having an optical sensor, an analog-to-digital converter, a plurality of computational elements, and an interconnection network. The optical sensor converts an object image into a detected image, which is then converted to digital image information by the analog-to-digital converter. The plurality of computational elements includes a first computational element having a first fixed architecture and a second computational element having a second, different fixed architecture. The interconnection network is capable of providing a processed digital image from the digital image information by configuring and reconfiguring the plurality of computational elements for performance of a plurality of different imaging functions. The invention may be embodied, for example, as a digital camera, a scanner, a printer, or a dry copier.

摘要翻译： 本发明提供一种具有光学传感器，模数转换器，多个计算元件和互连网络的数字成像设备。 光学传感器将对象图像转换为检测图像，然后通过模数转换器将其转换为数字图像信息。 多个计算元件包括具有第一固定架构的第一计算元件和具有第二不同固定架构的第二计算元件。 互连网络能够通过配置和重新配置用于执行多个不同成像功能的多个计算元件从数字图像信息提供经处理的数字图像。 本发明可以被实现为例如数字照相机，扫描仪，打印机或干式复印机。