公开(公告)号：US6025751A

公开(公告)日：2000-02-15

申请号：US947754

申请日：1997-10-08

申请人： Paul M-Bhor Chiang ,  Chia-Jen Chang ,  Hung-Mao Lin ,  Rita Au Hsu

发明人： Paul M-Bhor Chiang ,  Chia-Jen Chang ,  Hung-Mao Lin ,  Rita Au Hsu

IPC分类号： G11C8/08 ,  G11C11/408 ,  H03M7/162

CPC分类号： G11C11/4085 ,  G11C8/08

摘要： Aspects for self bootstrapping word-line driver circuitry are provided. In a circuit aspect, a word-line driver circuit for a memory cell in a semiconductor memory includes a signal input means, the signal input means comprising a first plurality of transistors, the first plurality of transistors receiving an input voltage signal higher than a voltage supply signal of the semiconductor memory. The circuit further includes a signal output means, the signal output means comprising a second plurality of transistors coupled to the first plurality of transistors and providing an output drive signal sufficient for the memory cell.In a method aspect, a method for providing proper voltage level output of a word-line driver circuit for a semiconductor memory includes forming a self-bootstrap circuit as the word-line driver circuit and providing an input voltage signal to the self-bootstrap circuit, the input voltage signal acting as a source voltage for the circuit and being higher by a predetermined value than a supply voltage of the semiconductor memory.

摘要翻译： 提供自引导字线驱动电路的方面。 在电路方面，半导体存储器中用于存储单元的字线驱动电路包括信号输入装置，信号输入装置包括第一多个晶体管，第一多个晶体管接收高于电压的输入电压信号 半导体存储器的供给信号。 电路还包括信号输出装置，信号输出装置包括耦合到第一多个晶体管的第二多个晶体管，并提供足以存储存储单元的输出驱动信号。 在方法方面，用于为半导体存储器提供字线驱动电路的适当电压电平输出的方法包括形成自引导电路作为字线驱动电路，并向自引导电路提供输入电压信号 所述输入电压信号用作所述电路的源电压并且比所述半导体存储器的电源电压高预定值。

公开(公告)号：US5898626A

公开(公告)日：1999-04-27

申请号：US879208

申请日：1997-06-19

申请人： Paul M-Bhor Chiang ,  Hung-Mao Lin ,  Chia-Jen Chang

发明人： Paul M-Bhor Chiang ,  Hung-Mao Lin ,  Chia-Jen Chang

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/83 ,  G11C29/84

摘要： Circuit, method, and system aspects for achieving redundancy circuitry programming in semiconductor memory are provided. Through these aspects, utilization of a circuit including a logic mechanism for receiving an enable signal and an address signal, a switching mechanism coupled to the logic mechanism for controlling delivery of the address signal, and a fuse mechanism coupled to the logic mechanism for allowing selective address programming responsive to the address signal in order to produce a desired logic level for a redundant address output signal occurs to form an address programming circuit. Further, selective input of an enable signal to the address programming circuit provides control of the address programming circuit to produce a desired logic level output. Additionally, integration of a plurality of the address programming circuits to form a redundancy programming circuit is achieved with each address programming circuit corresponding to one bit of an input address signal.

摘要翻译： 提供了用于实现半导体存储器中的冗余电路编程的电路，方法和系统方面。 通过这些方面，利用包括用于接收使能信号和地址信号的逻辑机构的电路，耦合到用于控制地址信号的传送的逻辑机构的开关机构，以及耦合到逻辑机构的熔丝机构， 发生响应于地址信号的地址编程以产生用于冗余地址输出信号的期望逻辑电平以形成地址编程电路。 此外，使能信号向地址编程电路的选择性输入提供地址编程电路的控制以产生期望的逻辑电平输出。 此外，利用对应于输入地址信号的一位的每个地址编程电路来实现多个地址编程电路的集成以形成冗余编程电路。

公开(公告)号：US6097649A

公开(公告)日：2000-08-01

申请号：US088426

申请日：1998-06-01

申请人： Paul M-Bhor Chiang ,  Jin-Man Han ,  Hung-Mao Lin

发明人： Paul M-Bhor Chiang ,  Jin-Man Han ,  Hung-Mao Lin

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.0 V without compromising the reliability of the sense amplifier. The implementation of the method and structure of the present invention is cost effective and practical for most if not all DRAM applications.

摘要翻译： 提供了一种用于在计算机存储器结构中具有高逻辑高电压的刷新操作的方法和结构。 该方法和系统首先将多个位线和多个互补位线预充电到高于参考电压的电压。 然后，选择多个字线和至少一个参考字线中的至少一个。 接下来，感测放大器被激活，使得多个位线或多个互补位线放电到逻辑低电压。 该放电在多个位线和多个互补位线之间产生电压差。 位线上产生的电压恢复到所选字线上的存储单元。 然后，将多条位线和多条互补位线恢复到参考电压。 该方法和结构允许使用低于2.0V的逻辑高电压，而不损害读出放大器的可靠性。 本发明的方法和结构的实现对于大多数（如果不是全部）DRAM应用是成本有效的和实用的。

公开(公告)号：US06820224B1

公开(公告)日：2004-11-16

申请号：US09542174

申请日：2000-04-04

申请人： Hung-Mao Lin ,  Jyh-Cherng Lin ,  Douglas Chen

发明人： Hung-Mao Lin ,  Jyh-Cherng Lin ,  Douglas Chen

IPC分类号： G11C2900

CPC分类号： G11C29/76 ,  G11C15/00 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/0401

摘要： Aspects for increasing yield in an embedded memory device are described. With the aspects of the present invention, a cache is provided for a memory unit of an embedded memory device. Attempts to access a failed bit memory location in the memory unit are determined. When a failed memory bit location is being accessed, substitution of a memory location in the cache for the failed bit memory location occurs.

摘要翻译： 描述了在嵌入式存储器件中增加产量的方面。 利用本发明的方面，为嵌入式存储器件的存储器单元提供高速缓存。 确定访问存储器单元中的故障位存储器位置的尝试。 当访问失败的存储器位位置时，发生高速缓存中的存储器位置发生故障位存储器位置的替换。