公开(公告)号：US6098176A

公开(公告)日：2000-08-01

申请号：US16788

申请日：1998-01-30

申请人： Paul William Coteus ,  Daniel Mark Dreps ,  Frank Ferraiolo ,  Gerard Vincent Kopcsay ,  Todd Edward Takken

发明人： Paul William Coteus ,  Daniel Mark Dreps ,  Frank Ferraiolo ,  Gerard Vincent Kopcsay ,  Todd Edward Takken

IPC分类号： G06F1/10 ,  G06F1/12

CPC分类号： G06F1/10

摘要： A clock signal distribution system is disclosed for providing synchronous clock signals to a plurality of electronic circuit devices. The system includes a clock signal generator means for providing a single frequency sinusoidal clock signal output and a plurality of electronic circuit devices. A clock signal distribution network including interconnected resonant segments of a transmission line 13 connected to the clock signal of the clock signal generator and to the plurality of electronic circuit devices for providing separate synchronous, phase aligned clock signals to the electronic circuit devices. The transmission line segments have lengths matched to the clock signal frequency wavelengths to eliminate clock signal distribution problems such as skew, jitter and pulse distortions.

摘要翻译： 公开了一种用于向多个电子电路装置提供同步时钟信号的时钟信号分配系统。 该系统包括用于提供单频正弦时钟信号输出的时钟信号发生器装置和多个电子电路装置。 时钟信号分配网络，包括连接到时钟信号发生器的时钟信号的传输线路13的互连谐振段，以及多个电子电路装置，用于向电子电路装置提供单独的同步相位对准的时钟信号。 传输线段具有与时钟信号频率波长匹配的长度，以消除诸如偏斜，抖动和脉冲失真的时钟信号分配问题。

公开(公告)号：US07312402B2

公开(公告)日：2007-12-25

申请号：US10269404

申请日：2002-10-11

申请人： Rafael Antu ,  Cathy Marie Drews ,  David A. Plomgren ,  Todd Edward Takken

发明人： Rafael Antu ,  Cathy Marie Drews ,  David A. Plomgren ,  Todd Edward Takken

IPC分类号： H05K1/16 ,  H01K3/10

CPC分类号： H05K1/0231 ,  H05K1/114 ,  H05K2201/0792 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49133 ,  Y10T29/49165

摘要： A method and apparatus that provides improved loop inductance of decoupling capacitors. Vias are moved close to the pads and close to each other. Instead of placing power and ground vias on opposite sides of the capacitor, these vias are moved around to the same side of the capacitor and are placed as close to each other as manufacturing tolerances will allow. For designs using standard two-terminal surface mount capacitors, two vias per capacitor, and standard manufacturing procedures (no vias inside pads, for example), the lowest possible loop inductance of the capacitor's connections to the printed circuit board planes is provided. This results in the lowest effective capacitor series input inductance.

摘要翻译： 提供去耦电容的环路电感的方法和装置。 通风口移动靠近垫子并彼此靠近。 代替在电容器的相对侧上放置电源和接地通孔，这些通孔被移动到电容器的同一侧，并且如制造公差将允许的那样放置得彼此靠近。 对于使用标准两端表面贴装电容器的设计，每个电容器有两个通孔，以及标准制造程序（例如，焊盘内部没有通孔），提供了电容器与印刷电路板平面连接的最低环路电感。 这导致最低有效的电容器串联输入电感。